You have gotten me through so many homeworks and tests it's not even funny! Trust me, I've been sharing you with my friends. Great job and thank you for posting these.
thank you so much for this video. absolutely perfect explanation with the "Has - Awaits". so simple and intuitive. Was struggling for 2 days to figure it out with normal university books. subscribed.
firstly I will like to appreciate the brain being all these videos, I want to confess that watching this videos have really changed my orientation about digital electronics. God bless u sir. please my request is that I will like to have a lecture like this using JK flip flop instead of DO flip flop. Thank u
+Neso Academy I will be the happiest man on earth if that could be done soon as possible bcause all your lectures has been interesting and it's really giving me confidence on my forth coming exam. thank u so much
I share the same thoughts, but is it correct? But if we only have 3 states, how do we come up with the state table as we need 2 Flip Flops. Maybe that's the reason for the s3.
When designing a sequence detector, but with Moore state machine, how do you get the output y (cause it shouldn't be dependant of the input x) ? In this case will it be just Qa ?
what would the finished clock look like at the end of this implemented circuit? I'm not certain if this would be synchronous, all coming from the same clock pulse, or asynchronous, or how to know. thank you so much for the amazing lessons and explanations. Your work makes a huge positive impact for me.
love your videos but this video and the previous one were extremely confusing. can you please explain more about overlapping and a more detailed explanation on how you got the state diagram?
I think when we are in S2 and input is 1, make output 1 which means we have detected 111 and get back two s2 which means we've already seen 11 and waiting for another 1. it's like slicing the adjacent 1s into windows of 111s.
but no , wait a min if you that you wont be able to write the 4 states as qa and qb are 2 varaiables of the present state and there must exist 4 states to complete the table
@@user-dz6zd9zk2f yeah, you can use QA QB X until 1 1 1 and when QA QB X = 1 1 0 and 1 1 1 or that means QA and QB is 1 1 respectively or when S3 happen, you assign QA+ and QB+ = X (don't care) because the S3 is unlikely to happen, thus if you use D Flip Flops you can assign QA+ = DA and QB+ = DB or when you use T Flip-Flop you can also assign TA and TB as X (don't care).
@@adeirman2705 Was looking for exactly this in the comments! Luckily i found ur conversation about it; was really confused why he uses 4 states in a Mealy where 3 would be enough.
in non overlapping case when four 1111 comes ,after three consecutive 1 was noted out put was 1.and again it started from next 1,but question was to find three or more consecutive no of 1's ,it makes a doubt that when four consecutive ones comes output should be 1 only or 0
I think there is a mistake in the output of nonoverlapping. when we first 001 then the output should be zero and after that, the next sequence should start and in the next sequence there are two 1's so the output should be zero again not 1. correct me if I'm wrong.
Won't just three states be enough for the sequence detector? at s2 state if next bit is 1 the next state is s2 itself and o/p is 1 Forever grateful for the playlist!
I do not understand: Is this a Moore Machine? If yes, then why is the output influenced by the input? If it is a Mealy Machine, then why is the number of states four while the number of bits is three?
I will not get the expected result if I design, sequential for the above state diagram. output y=Ax is the boolean expression we obtain, so it will not detect 3 or more consecutive 1's.
I don't understand why the non-overlapping output does not chose the four 1's at once... when the question contains 3 or more consecutive 1's. Why does it take only consecutive three 1's into consideration?
Actually here overlapping permitted so,from s2 when input is 0 it has to go to S1 state why because s2 has 1,it can start detection from s1 onwards. Pls let me know. More detail explanation is required there I hope so. Tq
Please put the presentation no with the presentation as it is very confusing that which presentation comes after which. Please tell me which presentation order in which i should watch the videos after introduction to state tables.
Can only 3 states (S0, S1, S2) be used in this case because when the 3rd 1 has to be detected, s2 state will be in s2 (1/1) and it will go to s0 for 0/0
@@nandinikasuba6673 since we have to find sequence like 1111111.... as soon as we got our first '1' we went from S0 to S1.....but after it if we get a '0' instead of '1' , like a sequence '010',our chain breaks and we have to start again from next '1' since we can't take previous '1', That's why we went from S1 to S0 to get that reset.... and i am answering this to a 1year old comment...lol
Sir why did you put two states on your state asignment when you were detecting a 3 bit pattern why did you find the kmap for Qa+ n Qb+ n not for Qa n Qb
It's been 8 years but still relevant, helpful and easy to understand
you are absolutely right brother.
Yeah bro
You have gotten me through so many homeworks and tests it's not even funny! Trust me, I've been sharing you with my friends. Great job and thank you for posting these.
thank you so much for this video. absolutely perfect explanation with the "Has - Awaits". so simple and intuitive. Was struggling for 2 days to figure it out with normal university books. subscribed.
Hands down the best resource on internet to learn Intro To Digital Logic, Thanks a bunch .
I would have failed my semester without your videos, really, thank you very much!
i am watching this three hours before my exams....you seriously saved me. Many thanks !!!
Just got a 97.5% on my final because of this channel.
Nerd
Kis clg me itne marks milte hai bhai 😅😂
Sayi
Itne toh agar phone aur book v dedo toh tabh v nhi aate
Bro ye konse school me kaha se sequence detector pada rahe he?
i passed my class because of you. thank you fam
firstly I will like to appreciate the brain being all these videos, I want to confess that watching this videos have really changed my orientation about digital electronics. God bless u sir. please my request is that I will like to have a lecture like this using JK flip flop instead of DO flip flop. Thank u
+Neso Academy I will be the happiest man on earth if that could be done soon as possible bcause all your lectures has been interesting and it's really giving me confidence on my forth coming exam. thank u so much
sir have you uploaded the same problem using jk flip flop....? it l b much useful fr me
Explanation is just amazing...no words to describe
There is no need for the state s3 , we can directly connect s0 with s2 for 0/0 and put a loop on s2 for 1/1.Correct me if I am wrong.
same thought here
I share the same thoughts, but is it correct? But if we only have 3 states, how do we come up with the state table as we need 2 Flip Flops. Maybe that's the reason for the s3.
fourth state of the F/F could just be a dont care, dont cares are possible in state table
Yes you're correct, it's a redundant state (therefore functionally equivalent to S2).
State reduction is explained in the next video itself.
thank you very much for this video. it really helped me..how i wish i have seen this before my midterms...you really are a good teacher...
Clear explanation. Amazing!
Im from Argentina and i study Engeneer Electronic you´ve saved my year with this videos! Congrats!! U has made an amazing job.
u r a life saver SIR!!!
thank you very much for the tutorials.i have learnt lot of things from your lectures.this covers my syalabus and this is very easy to understand too.
I have no words. Ur amazing👌👏😁
When designing a sequence detector, but with Moore state machine, how do you get the output y (cause it shouldn't be dependant of the input x) ? In this case will it be just Qa ?
Fantastic explanation broo..... Far better than coaching..
Thank you, this was very informative.
what would the finished clock look like at the end of this implemented circuit? I'm not certain if this would be synchronous, all coming from the same clock pulse, or asynchronous, or how to know. thank you so much for the amazing lessons and explanations. Your work makes a huge positive impact for me.
The explanation is too good.Thank you :)
My apny class fellows ko b ap ki tarah samjaya tha state machine thank u sir
you are a godsend for my engineering program holy shit
love your videos but this video and the previous one were extremely confusing. can you please explain more about overlapping and a more detailed explanation on how you got the state diagram?
mazza a gaya kya padate ho sir....u rock
Great video mate!
i want to say thank you so much for helping me in my digital logic exams! god bless you sir
Thank u..very useful video!!:)cleared many basic concepts
I truly love you man
Great, easily understandable, thanks.
thankyou sir..it was very helpful...Ur a great teacher..
extraordinary!!! very useful!! thank you for this video
Thank you for this video. You really helped me to understand.
Awesome..! Helped me a lot....
awesome, nice explanation
your videos are so helpful!!! thank you!!
mealy can be written in 3 states only, moore needs 4
Thnk you so much , It was very helpful in my Exam
In the S2 state if we get 1 as input we can take next state as S1 which will be easier since we will have only 3 states.
Really great video.. It helped a lot.
This video is extremely helpful Thank you for uploading!! :)
I think when we are in S2 and input is 1, make output 1 which means we have detected 111 and get back two s2 which means we've already seen 11 and waiting for another 1. it's like slicing the adjacent 1s into windows of 111s.
exactly the diagram should have only 3 states in total
but no , wait a min if you that you wont be able to write the 4 states as qa and qb are 2 varaiables of the present state and there must exist 4 states to complete the table
@@user-dz6zd9zk2f yeah, you can use QA QB X until 1 1 1 and when QA QB X = 1 1 0 and 1 1 1 or that means QA and QB is 1 1 respectively or when S3 happen, you assign QA+ and QB+ = X (don't care) because the S3 is unlikely to happen, thus if you use D Flip Flops you can assign QA+ = DA and QB+ = DB or when you use T Flip-Flop you can also assign TA and TB as X (don't care).
@@adeirman2705 Was looking for exactly this in the comments! Luckily i found ur conversation about it; was really confused why he uses 4 states in a Mealy where 3 would be enough.
in non overlapping case when four 1111 comes ,after three consecutive 1 was noted out put was 1.and again it started from next 1,but question was to find three or more consecutive no of 1's ,it makes a doubt that when four consecutive ones comes output should be 1 only or 0
Thank you for making my life so much easier!!!
+Xiaoyang Liu sn't s3 an extra state what if from s2 i go to s2 for 1/1 and to s0 for 0/0 and there is no s3
+Saumya Gupta Agree that
I think there is a mistake in the output of nonoverlapping. when we first 001 then the output should be zero and after that, the next sequence should start and in the next sequence there are two 1's so the output should be zero again not 1. correct me if I'm wrong.
Won't just three states be enough for the sequence detector? at s2 state if next bit is 1 the next state is s2 itself and o/p is 1
Forever grateful for the playlist!
Yeah you are right, even I was confused with that needless extra state
life saving videos!
your videos are so helpful, thanks a lot
Why we are not using a self-loop on s2 for 1/1,,, that would be easier without an extra state
Thank you sir
The state diagram u hv drawn is for Overlapping??
Hat's off man
Thank you very much for the video !
I do not understand: Is this a Moore Machine? If yes, then why is the output influenced by the input? If it is a Mealy Machine, then why is the number of states four while the number of bits is three?
S3 state is not needed
Thank you very much ... it can be reduced to 3 state... thank you again ...
thank you soo much for the video i just want to know whether we can use any gate to impliment the assigment table or not
i am confused with overlapping and non overlapping ..... please suggest me with eg such as 1101 , 11001,1010 how to draw state diagram
with hands holding a working pen and paper. Most imp, a tiny bit of thinking (if you have) ;)
Dude some one replying after 4yrs seriously .....i am passed on but whatever thanks ☺
But still dude you dont understand my question ....try some common sense haahaa
And u still a nerd after all lol
very nice lecture sir
Doubt 12:15 why did he take Qa , xQb on k map rather x , QaQb
Bata deta bhai par teri exam ab ho chuki hogi jandee hard luck
state c and state d are identical
so can we reduce them ??
and if we can , how will we draw the state table??
True ... i try to solve it before him and had reduced it to 3 state only ...
connect s0 with s2 for 0/0 and put a loop on s2 for 1/1
thank you sir for your videos ❤ sir we can detect the same problem by 3 states only .
can you kindly answer how it is determined that we need 2 D-flipflops to implement this circuit>?
final tomorrow. you saved me. thanks man
+Samario Torres lol were both in the same boat
+Samario Torres same here
+Samario Torres one more here
can u teach me this?
Is there really a need for the S3 state? The S2 can keep producing high output as long as the next bit in the bitstream is 1 right?
Yes there is no need for s3
This is why we need to use state reduction before designing the circuit
please upload a video for sequence generator
if we create a self loop at s2 with input 1 and output 1 then we wouldn't have to use state s3,right?
Sir there is no. Need for DA and DB K-map. Because DA=QA+ and DB=QB+.So we can directly write them from next state.Are I right ?
really nice explanation.. but I just want to ask that how do we know that
how many states are required for sequence detector..?
it depends on how many bit of the input sequence you want to detect
I will not get the expected result if I design, sequential for the above state diagram. output y=Ax is the boolean expression we obtain, so it will not detect 3 or more consecutive 1's.
So do we have to do state reduction?
I don't understand why the non-overlapping output does not chose the four 1's at once... when the question contains 3 or more consecutive 1's. Why does it take only consecutive three 1's into consideration?
Excellent
You miss the state reduction step? Because i am getting different solution.
plz do sequence generator also
why did u take s0 till s3 cant it be done from s0 to s2 right ?
nice and thank you !
Actually here overlapping permitted so,from s2 when input is 0 it has to go to S1 state why because s2 has 1,it can start detection from s1 onwards. Pls let me know. More detail explanation is required there I hope so. Tq
Plzz make a video on sequence generator also
Overlapping is confusing me. since more than three is mentioned ,so for non-overlapping case 1111 output is why 0?
And please try to answer questions of all the people, and thank you for such awesome teaching.
Using D flip-flops, design a circuit to generate a pattern 0-4-6-7-3-1 without using any additional logic gates.
input can be any random set of the binary numbers.......
please reply....
Please put the presentation no with the presentation as it is very confusing that which presentation comes after which. Please tell me which presentation order in which i should watch the videos after introduction to state tables.
s2 and s3 can be merged into 1 state.
Can only 3 states (S0, S1, S2) be used in this case because when the 3rd 1 has to be detected, s2 state will be in s2 (1/1) and it will go to s0 for 0/0
what will be the case if we use t flip flop instead of d ?
Sir, can u please explain why S2 and S3 are not reduced to one state by state reduction method? Thanks a lot for these videos
Yes I am also thinking so, it can be done with just 3 states as well, seems like this is an error.Hope Neso Corrects it soon.
True
at 5:18 why s1 goes to s0?doesn't it go to itself?please answer
It's not an error. Just extra hardware. It will work in either case.
@@nandinikasuba6673 since we have to find sequence like 1111111.... as soon as we got our first '1' we went from S0 to S1.....but after it if we get a '0' instead of '1' , like a sequence '010',our chain breaks and we have to start again from next '1' since we can't take previous '1', That's why we went from S1 to S0 to get that reset....
and i am answering this to a 1year old comment...lol
Sir....In this example...Whether you have considered overlapping or non overlapping?...I am very confused!
over-Lapping ....
What about flipflop
Which flipflop are you using??
Thank you
Why did u consider output values for realization
thanks for all sir , but
on the state diagram why the output is " 0 " when we go to s3 to s0??
sir, i have a doubt... why did u use negative edge triggering
If multiple inputs are considered ie., 010, 101 are taken
That was great!
How could u consider input sequence
state reduction was possible right?like s2=s3??
Sir why did you put two states on your state asignment when you were detecting a 3 bit pattern
why did you find the kmap for Qa+ n Qb+ n not for Qa n Qb
As we are having “ three or more consecutive 1” in question . So in non overlapping case too .. wouldn’t there be 11 in the last ..
Yeah i too felt same