BRO U R EXPLAINATIONS ARE REALLY AWSOME CLARIFYING MANY DOUBTS PLS DO SOME REAL TIME PROJECTS LIKE REAL TIME CLOCK,TRAFFIC CONTROL SIGNAL WHICH WILL BE MORE BENEFICIAL
So the difference in melay non overlap we will go back to idle state no matter if it's 1or 0 input for the last state else everything is the same process for overlap & non overlap. Pls respond so it would clear the doubt. Thanks
😎 Rambo Namaskaram 🙏, thats to long sequence , you draw it similar to the one I have shown ,but don't use circles for state representation , instead u can use single line to represent a state shown below S1 -------------------------- S11 -------------------------- ......so on and show transitions . Thanks for asking Rambo🤝, good luck and great health 👍😊, take care.
In non overlapping, why do we go to IDLE state from S1101 on recieving 1 but not going to IDLE state from S11 on recieving 1. Or why dont we go to S1 or S11 from S1101 on recieving 1? Its all the same questions just asked in different perspectives. Please let me know
@@KarthikVippala different mux designs,tricky questions on counter frequencies, propagation delay of both synchronous and asynchronous counters,etc for more depth just give reply I will send all the crazy questions to your mail.u can Edit those bunch of questions into one vedio..by keeping a good title "digital electronics tricky interview questions" or something that is up to u. make something better than other TH-cam channels..compare their vedios, likes n rectify their mistakes in your vedios.definetly one day the channel becomes more successful...🎉🎉
Can you also explain us how to make a FSM which gives output 1 only when total is divisible by 5 otherwise 0. The input is an infinite bit stream with LSB first.
Namaskaram Ankita 🙏 , thanks for asking FSM will have 3 states idle, divisible by 5 & not divisible by 5 . To move to either state from idle we will check the divisibility . Good luck, great health 👍😊
@@KarthikVippala Thanks for the response. But how do we check the divisibility if input stream is infinite (with every clock pulse one bit is coming and we have to check the divisibility of entire stream)
@@KarthikVippala Yes we get one bit per clock cycle and the first bit is to be taken as LSB. The exact statement is "Suppose you have an infinite bit stream representing a binary number (LSB first), and that stream is entering your machine one bit per clock cycle, and you want your state machine to output a 1 any time the total is divisible by 5, otherwise output zero."
Don't focus on pronunciation,u were looking but hurry in non overlapping
Noted will improve on it🤝
in the equations shown at 11:44 you have exchanged D0 with D2 as D0 is for Y0+ and D2 is for Y2+. Please correct it.
sir in non overlap 11011, why dont we add an extra state s11011 but instead go directly to idle? plz explain
Explanation is very clear and straight forward .thank you
BRO U R EXPLAINATIONS ARE REALLY AWSOME CLARIFYING MANY DOUBTS PLS DO SOME REAL TIME PROJECTS LIKE REAL TIME CLOCK,TRAFFIC CONTROL SIGNAL WHICH WILL BE MORE BENEFICIAL
Thank you🙏
So the difference in melay non overlap we will go back to idle state no matter if it's 1or 0 input for the last state else everything is the same process for overlap & non overlap. Pls respond so it would clear the doubt. Thanks
Namaskaram 🙏 Manoj, hope you're doing great, you are correct, good luck & great health 👍😊
@@KarthikVippala thanks Karthik
That's pretty impressive bro , thanks for the clarification...👍👍
Namaste 🙏 kamlesh , thanks for the support, good luck & great health 👍😊
Before I watched this video , I can't solve any q/s about this topis .Thank you very much ! :)
Namaste 🙏, thanks for the support, good luck and great health 👍😊
Hey Karthik I have the doubt in non overlap S11. Can you please justify it for me?
boss... how to find using 1111010 for melay using flip flops
😎 Rambo Namaskaram 🙏, thats to long sequence , you draw it similar to the one I have shown ,but don't use circles for state representation , instead u can use single line to represent a state shown below
S1 --------------------------
S11 --------------------------
......so on and show transitions .
Thanks for asking Rambo🤝, good luck and great health 👍😊, take care.
how to with 11010 pls help me
Namaste , its similar to the one presented , we need to change the last bit to 0 .
Thanks for asking good luck & great health :)
@@KarthikVippala Thank u so much!
i can do it.
Sir, is sequence detector an application of fsm?
Yup, good luck, good health 👍😊
sir, why did u pop a *S1 at 9:54 , any mistake or correction you want to indicate?
I think it's a bug 😬 , thanks for pointing out.
Do good & be healthy 👍
@@KarthikVippala haha thanks sir... the video is really awesome 😍💥
@@rohitkumarvarma4952 your welcome 🙏
Its really great!...you are using: same question in both case (overlap and Non overlap). ...keep it on.
Thank you hemchand ,I have used the same question for both.
Good luck, good health 👍
I mean its great. You have used same question in both case....
thank you. its really help me a lots in understanding the concept mealy
Thank you🙏
Sir at 14:09 why we stay at S11 when we have an input 1 since we r using non overlap g.. I think it starts from IDLE
Namaste🙏, Rahimul,thanks for asking ,
From s11 state we start the pattern "11" again , so need not go back to Idle .
Good luck, good health👍😊
@@KarthikVippala but isn't it non overlap condition ??
if we get 1 then we should go back to the S1 state
Hello sir, Could you explain in what manner you are taking the input sequence for 11011.
Thanks for the video i asked this concept to you already thanks bro superb bro.
Your welcome ganesh , took some time , thanks for being patient.
Good luck, good health 👍
so confusing
Where?
sir please one example of pulse stretcher by D-FF with proper inputs
sure will make it , thanks for suggestion, excuse me for not answering all your comments,good luck & great health :)
Explanation is very clear and straight forward..thank you
Hello sir, @13:54 shouldn't it go to the S1 rather than IDLE?
Namaskaram zenith chokshu🙏, we need to go IDLE , because sequence is not having 10 to start.
Thanks for asking, good luck & great health 👍😊
sir level h
In non overlapping, why do we go to IDLE state from S1101 on recieving 1 but not going to IDLE state from S11 on recieving 1.
Or why dont we go to S1 or S11 from S1101 on recieving 1? Its all the same questions just asked in different perspectives. Please let me know
Great video, thank you so much 👍
Your welcome, good luck, good health 👍
in overlapng why did you go to s11 instead of s1 to reduce
Sir instead of going sequence 11011 can we take this as 3 bit 110 .
Namaste 🙏 ravindra , Yes you can if you want a 3 bit 110 sequence and change the states accordingly. Good luck & great health 👍😊
Hi sir,
What will be melay diagram for 10110
Namaskaram Nanditha 🙏 , pls try , if you are stuck I will help you .
Good luck & good health 👍😊
@@KarthikVippala Sir, I have understood everything. But once solving all forward cases, how to do left over cases. That one I am not getting.
Honestly very informative!!!!
Thank you so much🙏😎
Sequence detector 11010 with 8 states
Thanks bro😊😊🙌🙌
Your welcome🙏
1st like .1st comment. Sir make some interesting vedios on digital design (basic)...
Thank you sharath 👍
Please suggest some topics 👍
@@KarthikVippala different mux designs,tricky questions on counter frequencies, propagation delay of both synchronous and asynchronous counters,etc for more depth just give reply I will send all the crazy questions to your mail.u can Edit those bunch of questions into one vedio..by keeping a good title "digital electronics tricky interview questions" or something that is up to u. make something better than other TH-cam channels..compare their vedios, likes n rectify their mistakes in your vedios.definetly one day the channel becomes more successful...🎉🎉
Hmmm...make videos on basic important topic.
@@hemchandjain2189 suggest basic topics , I will look into it
hi, how to find sequence for non decimal value like 102210 ?
Convert it to decimal and the follow normal procedure
Very neat explanation sir, thanku so much
Namaskaram Thummala 🙏 , thanks for the support and love, good luck & great health 👍😊 take care.
Why 6 bit is 0
Can you explain Transition table also
Can you also explain us how to make a FSM which gives output 1 only when total is divisible by 5 otherwise 0. The input is an infinite bit stream with LSB first.
Namaskaram Ankita 🙏 , thanks for asking FSM will have 3 states idle, divisible by 5 & not divisible by 5 . To move to either state from idle we will check the divisibility . Good luck, great health 👍😊
@@KarthikVippala Thanks for the response. But how do we check the divisibility if input stream is infinite (with every clock pulse one bit is coming and we have to check the divisibility of entire stream)
Do we get one bit for one clock cycle or entire bits?
@@KarthikVippala Yes we get one bit per clock cycle and the first bit is to be taken as LSB. The exact statement is "Suppose you have an infinite bit stream representing a binary number (LSB first), and
that stream is entering your machine one bit per clock cycle, and you want your state machine to output a 1 any time the total is divisible by 5, otherwise output zero."
please check transition graph that accept binary numbers divisible by 5.
Can you give reply to the qn you asked at end
have u tried
@@KarthikVippala yes I haven't understood why it was done so
In Melay Non- overlap, why the state remained in S11 even if the ip came to be 1