Xilinx IP cores for DSP: FFT and IFFT

[@dandyroth]

I enjoyed the music, made it relaxing and easier to concentrate :)

[@matthewseals8110]

Very helpful. Thank you for sharing!

[@bassamalghram7506]

it is very good, but a small problem is the music sound in the background, which make it noising for us.

[@mumar3]

Sir can you please guide me how you entered the input signal into the fft ipcore? did you enter random values in the testbench? I shall be very grateful if you could make a video on this,as for my final year project im trying to integrate an adc with the fpga and perform fft analysis.

[@cricket_ki_duniya3237]

Hi , Can you share the IFFT configuration with 12 Channel for 512 point size. I have tried but my plots are not proper.

[@saleemullah7495]

Kindly explain fft ip core settings for fft and ifft by using 16 bit counter as input to fft core and prove that by taking ifft ,the same counter values are recovered. Thanks in advance

[@farbius85]

And the IP core can be easy rebuilt from FFT to IFFT

[@saleemullah7495]

@@farbius85 ok what is setting from FFT to ifft .

[@myetis1990]

@@saleemullah7495 if you configured the IP as runtime configurable then 2:51 set the FWD/INV bit from s_axis_config_tdata. (bool 1: FFT 0:IFFT)

[@madarauchiha9834]

Hello, thnx for the video. How i can find Design block of this project?

[@elsiesemico]

How the input signal is specified? Are these samples from an ADC? how they transformed before they feeded to the ip block? Thank you!

[@farbius85]

The signal was simulated. There is no additional transformation, just compatibility to FFT IP core ( 16 bits for real and imag part )

[@elsiesemico]

@@farbius85 for signed fixed point integer inputs, samples of an adc, the imaginary part will be always zero? Thank you

[@farbius85]

@@elsiesemico yes, imaginary part can be zero.

[@2011HPS]

Hi, How can we add CP length :)

[@omidmobini8960]

can anybody help me?
how we could see Real and imaginary input and output in waveform however in verilog aren't defined

[@farbius85]

@@omidmobini8960 please clarify your question. What does it mean “output and input in Verilog aren’t defined”? Verilog is a language. You can define smth in a file (test bench for example) by using Verilog, VHDL or SV. Or maybe you are trying to extend Verilog standard …

[@omidmobini8960]

@@farbius85 thank you so much for pay attention. I mean in sim waveform in video we see InRe, InIm and outRe, outim but in my waveforms i can not see! could you plz help me to see these waveforms?

[@omidmobini8960]

@@farbius85 could you please say how to see InRe and InIm waveform?

[@farbius85]

@@omidmobini8960 digilent.com/reference/programmable-logic/guides/simulation

[@THLi-uo5kq]

Hi,sir, l wanna know why my output datas from fft ip core are wrong, and my input datas are from PS, use C struct to store real and imaginary ,and both of them are type of uint16_t. Not all my output datas are wrong but many of them are 0xfffe or 0xffff , l wonder if my ip core configurations wrong ? So plz give me some advice ,thx.

[@THLi-uo5kq]

My input datas is true , l am sure. And my ip cores configuration is scale, fixed , and input data width is 16 , Natural

[@THLi-uo5kq]

In addition, my input data is updated from adc.

[@farbius85]

I would check input of the IP core with System ILA and scaling schedule. Also I would pay attention on fixed arithmetic: signed or unsigned.

[@LL-ue3ek]

Why do you add background music? it's like turning on music in a lecture room, what would the professor and students do? I left the video immediately.

[@farbius85]

Thanks for the remark, I’ll take it into account in the next lessons !