This is the best lecture I have ever seen on this topic. I am really grateful to the professor who has explained every bit of the circuit in such a detailed and simplest possible way.Thank you sir.
This is no doubt the best lecture ever on TTL NAND gate. I searched so many videos, no video ever explained so beautifully. Thanks sir for such a beautiful lecture
V_BB being 0.9 volts can still render the BJT to be in the Forward-Active mode, it solely depends on the ratio of R_B and R_C, in which context you are talking, sir?
Sir at 39 minutes, when you are talking about T4 getting cut-off due to the divided 0.75 volts between the base-collector and diode pn-junctions, why can't the 1.4 k ohm resistor drive T4 into saturation?
Because when current flows through T2's BE and then through T3's BE junction, both transistors are turned on which allows current to flow from the collector of T2, through T3 to ground, so the T2 collector voltage (T4 base voltage) will not rise above the two transistor's PN junction drops.
when emitter base junction is in forward biasing and base collector region in reverse biasing...then that condition of transistor is called as active or normal region...
Sir I have a doubt It is needed to connect negative terminal of the power source to A and B . so we'll draw or extend the same line to the base emitter source required so that we donot require a seperate source and essentially as an assumption , pn jn voltage is same as the emiter base voltage , so i think it works in controlled conditions Thankyou for a good lecture , Feeling curious for an Answer
@7:04 How is it saturation region? Vcc connects to collector which Is n side and 0.9 V is supplied to the base region which Is p type which means CB junction Is Reverse biased. So the region is active region right and not saturation?
braveknight 9 do you mean base of T4 /collector of T2??? If that's your questions then it's because of T2 being in saturation it has 0.2V across its C and E terminal and there is a 0.75 volt at terminal E because of T3 being on, it has 0.75v across its base and emitter terminals. So net voltage at collector of T2 is voltage across C and E and voltage at E= 0.2+0.75=0.95V
This is the best lecture I have ever seen on this topic. I am really grateful to the professor who has explained every bit of the circuit in such a detailed and simplest possible way.Thank you sir.
This is no doubt the best lecture ever on TTL NAND gate. I searched so many videos, no video ever explained so beautifully. Thanks sir for such a beautiful lecture
Extremely clear explanation, that too in accordance with Mano's Digital Design book! Life saver!
The best explanation of a TTL circuit.
phenomenal explanation ! Thank you Prof for such an interesting lecture !
From vietnam
best lacture for TTL logic on you tube thanku sir
OMG !! He's awesome !! i am preparing for my exams and he is a savior!!
amazing sir....now i understood the fund of saturation....pls keep posting such videos....
very interesting and amazing lecture
Thank You ! The best explanation of a TTL circuit.
Best lecture on TTL logic....
it was very easy and informative sir , Thank u so much , keep posting videos it will be of great help
VERY GUD EXPLANATION ND INFORMATIVE, PLS UPLOAD SUCH VIDEOS SIR THESE ARE VERY USEFUL .
Very informative ,best lecture on this topic!
vry well delivered class...thank you sir...u are helping lots of students...thaank you again...
This is the best lecture......
Great lecture. Very helpful. Thank you
Suhad Hadad t
Wow!!!😍😍😍so much to learn !!
Now I know about TTL clearly thanks sir
superp sir.....got my concepts crystal cleared nw!!!
Thank you, this is a great lecture!
awesome very well explained :) makes all sense for me now ;) got exames the day afther tomorrow :D tyvm!!
thank you sir very helpful for me!
superb lecture......so easily explained
Kudos to explanation 😃
Thank you sir you have cleared all my doughts
Very well explained.. Thank you sir..
Well Delivered. Well elaborated.
great lecture!!!
V_BB being 0.9 volts can still render the BJT to be in the Forward-Active mode, it solely depends on the ratio of R_B and R_C, in which context you are talking, sir?
Thank you very much sir.....
thank you, very good elaborate explanation
concepts got cleared , thank you sir :)
Thanks for the explanation.
Thank you sir, very clear
Perfect lecture, keep up the good work
Thanks :D! Im studing this things in german and i still dont have that high level on german to understand all.
Thank you so much, very helpful
very nice explanation...
THANKS A LOT SIR
great sir........
Very clear and straight to the point.
very good explanation
definately score 99/100 thanks proff.
First time seeing reveese active operation
excellent lecture sir
very clear explanation thnx
use vlc via tubemate or directly by link
enjoy ics
Thank you, very helpful class :D
Very well explained:)))
I so wish I was in IIT M.
Really good!
Excellent
Very nicceeeee
Sir why we use diode
All about that CRAZY MUSIC!
i so wish i was in one of the reputated institute like iitm...🙂
Superb lecture!
helpful...thanks sir.....!!!!
Gajab sir hai ,,, nsit me bhi aise teacher ho
thank you soooooooooooo much :)
Sir at 39 minutes, when you are talking about T4 getting cut-off due to the divided 0.75 volts between the base-collector and diode pn-junctions, why can't the 1.4 k ohm resistor drive T4 into saturation?
Because when current flows through T2's BE and then through T3's BE junction, both transistors are turned on which allows current to flow from the collector of T2, through T3 to ground, so the T2 collector voltage (T4 base voltage) will not rise above the two transistor's PN junction drops.
great...
Thank you! Very helpful! ;)
Well explained
Thanks Ted Bundy for this amzing lecture!
inverter, alright. ok. alright. ok.high input ok. nand gata ok. low input ok.
41:23 , 0.95 is shared actually
Does he mean Forward Active mode , when he says the transistor is operating in the normal mode?
when emitter base junction is in forward biasing and base collector region in reverse biasing...then that condition of transistor is called as active or normal region...
Thank yoy sir
nice lecture
excellent very clear thank u for sharing u knowledge
thanks sir :)
🙏🙏🙏🙏🙏🙏🙏🙏🙏
Good title song sir
Sir I have a doubt
It is needed to connect negative terminal of the power source to A and B . so we'll draw or extend the same line to the base emitter source required so that we donot require a seperate source and essentially as an assumption , pn jn voltage is same as the emiter base voltage , so i think it works in controlled conditions
Thankyou for a good lecture , Feeling curious for an Answer
@7:04
How is it saturation region? Vcc connects to collector which Is n side and 0.9 V is supplied to the base region which Is p type which means CB junction Is Reverse biased. So the region is active region right and not saturation?
g oo d
40:19 . can anyone help me to say when t2 is saturation how the collector of t4 become 0.95v
braveknight 9 do you mean base of T4 /collector of T2??? If that's your questions then it's because of T2 being in saturation it has 0.2V across its C and E terminal and there is a 0.75 volt at terminal E because of T3 being on, it has 0.75v across its base and emitter terminals. So net voltage at collector of T2 is voltage across C and E and voltage at E= 0.2+0.75=0.95V
Sir, ek IC KA 7632 standby mode me hai. Is IC ko TTL input se bina remote control ke kaise ON karen?
Does anyone know what year this is?
sir icrease ur speed
rajan goyal ok alright
In 47 min he used 30 min in saying okay
haha sahi me
Deepak Agrohia yes
same here
i think its too tough for u to admit ur laging
but dude its true
titu
your intro is too long
5.46 he taught by middle finger
Professor looks like poppat lal 😂😂😂🤐
Sorry
kuch bhi samaj me nai aya.
Kuch nhi samja bhai. Chuna laga dia mb waste ho gye
itna accha samjhaya lol
very nice explanation
Thnk u sir
Good lecture