Introduction to RTL | Hands on Verilog Programming | AND Gate Verilog Code | Lecture-1

[@JAI_BALAYYA_]

❤I love this concept

[@TechbuggyOfficial]

Thank You Bro👍

[@TechbuggyOfficial]

AND Gate Functionality Video:
th-cam.com/video/gAM9gFSV8Rg/w-d-xo.html

[@jyothi648]

Gud luck🤝..keep going..❣

[@TechbuggyOfficial]

Thanks👍

[@lokesh6908]

Very useful content..🤩🙌..keep doing like this..🙌..

[@TechbuggyOfficial]

Thanks Bro👍

[@MRG09]

Module and_gate(a,b,y);
input a,b;
output y ;
Module and_gate(input a, input b, output y);
What is the difference which one is better to use

[@TechbuggyOfficial]

In total we have Three ways of declaring port lists:
1. ANSI Style Port List.(it provides clear separation of port list elements)
Ex: what I taught in video.
2. Non-ANSI Style Port List.(it is used for smaller designs having less elements)
Ex: what you posted in the comment section.
3. Interface based Port List.(it provides reusability for complex interfaces)
Ex: Here we can define the interface port lists.
We can use based on our requirement of designing.
We can declare ports as input, output and inout ports also.
Thanks👍