The best video about verilog for beginners out there!! I' ve seen many of them that are 20-40 minutes long and i couldn't understand a single word. Great work bro!!!
even though it isn't a programming language, it is very similar to object oriented languages class -> module wire -> variable module adder(o,x,y) -> constructor this is very similar to c++. your explanation is amazing!! thanks for putting in so much effort
as a computer science student I was researching about vhdl, after around 10 hours of reading and watching I decided to check how verilog works and found this video. I think I might want to learn verilog instead.
Very good introduction, thanks. It somewhat begs the questions "wires?". Why not do it in the proceedural way of simly passing the output of one function (module) into the input of another? Having the wire declared independently looks like it can cause problems.... surely it allows you to have the one wire as the output of more than one module? Why have a language grammar which allows you do that by having a wire exist as a seperate entity to the inputs and outputs? Whilst a wire is exactly that in the real world... independent of the circuits you put it in... in the world of circuit design you don't want wires to be floating around on their own.
Wow an amazing way to explain such sensitive language for the dumbs like me.. Please give me more links of your video I wanna learn whole RTL from you.
This short 5 minute video is the best available on verilog
Dude even after 7 years i would agree to that
Yes
After 10 years still holds true
The best video about verilog for beginners out there!! I' ve seen many of them that are 20-40 minutes long and i couldn't understand a single word. Great work bro!!!
Pretty intuitive, this should be the best Verilog introduction video ever.
This video is the BEST way to understand a whole frickin topic in 5 mins. Literally the best video for beginners
Very well organized! This is the most coherent description I've found. Thanks!
I have been searching for this exact video for three days you are an absolute lifesaver thank you
excellent. absolutely excellent! Love the simplicity in the explanartion and the straight fordwardness
One of the best video got so far, clear, crisp..
Excellent video ! I been trying to learn verilog for a while and this really helped me understand it better.
Sir, thank you so much! Your video was not only helpful but gave me an excellent start to my verilog learning experience.
Excellent explanation thanx
the best video about Verilog, the vlogger is smart for sure.
The quickest video to understand what the Verilog is. Thx.
Shortest, simplest and best explanation on Verilog!
This video refers to structural hardware description, but hardware description languages also provide rtl description
The best verilog tutorial I ever seen :)
This is the best organized video........take love
This video will definitely save my test *peace*
Thank you so much it simplifies the core of understanding Verilog with in 5 minutes👏
You sir a amazing! I thought they only taught VHDL in the midwest, but I guess I'm wrong.
even after years still the best. bless your soul
you're a legend mate
RESPECT BROTHER !!! 4 min video>>>>prof's 1 hour lecture
Simple and on the point! Best explanation
THANK YOU! The visual aids helped alot!
This video is the best video about verilog which i understood clearly.
even though it isn't a programming language, it is very similar to object oriented languages
class -> module
wire -> variable
module adder(o,x,y) -> constructor
this is very similar to c++.
your explanation is amazing!! thanks for putting in so much effort
Woah man! Thank you so much!!! 😊 Really appreciate your efforts!
amazing, love the quick bite info style tysm
Thank you for your simple and understandable video.
great start, I wish there was a full course
Very concise and clear description!
Sir your explanation is best you should must make more videos on verilog as well as system verilog and UVM
Beautiful !!! The world needs more FPGAs
Amazingly concise and so beginner-friendly
You know what TH-cam, next time put this video as the first suggestion for Verilog. Not some company videos nobody will easily understand.
Sir I am beginner simple study and systematic way cleary explain.thanks lot
waw...superb teaching technique....thank u
best video i found for verilog. More please
extremely well explained. Thank you sir :)
awesome 5 minutes of my life searching here and there for verilog basics
This is the best short video for verilog basic
Thank you so much . You are awesome!!!
Great short description of Verilog
Wow this was super helpful!!! Thank god i got to this before my exams came up
Amazing Video !
Btw, Really shocked when i knew that Verilog does not describe bedrooms :"D
Oh my God. Thank you. Seriously
You just crushed it bro.
Thanks! Excellent explanation.
Exceptionally good intro. Nicely done.
Thanks for solving my doubts about verilog
Really wonderful expanation ..
Very well explained. Thank you. Can you make more ruboost tutorial about Verilog.
very easier beginning for learner. thankyou sir...
Amazing Video Sir! Kindly make such a video on VHDL
such a great explanation, thank you
Awesome!!! Thanks a bunch!!!
😂😂I watched 4 videos on verilog ,and this single video explained content of those 4 videos. Superb explanation.
Best Video Ever U seen About Iverilog
Excellent bro.. ❤️👑
Thanks ! Your explanation was clear !
Best video for beginners.
Great video, I learned more about verilog!
this is awesome... sir
Fantastic, thank you!
Very good introduction to Verilog !
as a computer science student I was researching about vhdl, after around 10 hours of reading and watching I decided to check how verilog works and found this video. I think I might want to learn verilog instead.
Very well presented ...
Okay, this was amazing. Thank you
This is amazing!
Wow, now I understand what Verilog actually is, thanx!
it tok me exactly 5 mins to understand . nice job
Thanks, It was very clear.
Best video for verilog
Very good introduction, thanks.
It somewhat begs the questions "wires?".
Why not do it in the proceedural way of simly passing the output of one function (module) into the input of another?
Having the wire declared independently looks like it can cause problems.... surely it allows you to have the one wire as the output of more than one module?
Why have a language grammar which allows you do that by having a wire exist as a seperate entity to the inputs and outputs?
Whilst a wire is exactly that in the real world... independent of the circuits you put it in... in the world of circuit design you don't want wires to be floating around on their own.
impressive and informative!
really cool video, thanks :D
Excellent video
amazing video
that was great !, dont u have a playlist on verilog coding /xilinx ??
superb video thank you thank you thank you so so much :D
Wow an amazing way to explain such sensitive language for the dumbs like me.. Please give me more links of your video I wanna learn whole RTL from you.
AWESOME!
Best video ever
plz make more videos..
Been reading websites about Verilog. Why can't websites explain any clearer like your videos. Thanks!
Спасибо)
Nice video, do more
very good, thanks
Thank you bro
excellent...
beautiful
Thank you so much!!!!!!!!!!!
So nice thanks
thnx for adding this
Awesome
GREAT!
why are you stopped making videos on verilogs, its so nice with great and relateble examples
Thks
thats so good