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Hi, thank you for sharing the video! But how did you create .veo file through IP Catalog? I followed your steps and got .vdh file instead. Do you have any solution about this?
Use tool GVIM to create that file , or i think u can create that file with notepad++
hi, sir can u share how to generate ip bram in verilog i tried generating it but it is generating in vhdl
After creating IP you find two files were created nor with VHDl and another with Verilog check for that
Sir, is this block generator is enough for display an image on vga monitor?
It's only a procedure for adding data to BRAM according to ur application
Hi, thank you for sharing the video! But how did you create .veo file through IP Catalog? I followed your steps and got .vdh file instead. Do you have any solution about this?
Use tool GVIM to create that file , or i think u can create that file with notepad++
hi, sir can u share how to generate ip bram in verilog i tried generating it but it is generating in vhdl
After creating IP you find two files were created nor with VHDl and another with Verilog check for that
Sir, is this block generator is enough for display an image on vga monitor?
It's only a procedure for adding data to BRAM according to ur application