What kind of testing do we do as of today for stacked dies? Is it just scan chain for purpose of connection checking? Or do we try to access some status/debug registers of IPs on the die? or do fault/error injections in one of the dies? Just wanted to understand what is the level of depth we go in for testing after fabrication. P.S.: My question maybe very basic as I am a SoC Verification Engineer on the frontend side and I am not aware of all the backend testing and intricacies.
5.5D design is ideal for stacking a CPU/ML die with a GPU die then having a IO/Memory die to the side Has anyone tried a punch card sale die design that lines up holes subject to thier compass direction?
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What kind of testing do we do as of today for stacked dies?
Is it just scan chain for purpose of connection checking? Or do we try to access some status/debug registers of IPs on the die? or do fault/error injections in one of the dies?
Just wanted to understand what is the level of depth we go in for testing after fabrication.
P.S.: My question maybe very basic as I am a SoC Verification Engineer on the frontend side and I am not aware of all the backend testing and intricacies.
5.5D design is ideal for stacking a CPU/ML die with a GPU die then having a IO/Memory die to the side
Has anyone tried a punch card sale die design that lines up holes subject to thier compass direction?
Nice
its work jumping curent