Testing 2.5D And 3D-ICs

Disaggregating SoCs allows chipmakers to cram more features and functions into a package than can fit on a reticle-sized chip. But as Vidya Neerkundar, technical marketing engineer at Siemens EDA explains to Semiconductor Engineering, there are challenges in accessing all of the dies or chiplets in a package. The new IEEE 1838 standard addresses that, as well as what to do when 2.5D and 3D-ICs are combined together in the same package.

[@lumorningstar6178]

What kind of testing do we do as of today for stacked dies?
Is it just scan chain for purpose of connection checking? Or do we try to access some status/debug registers of IPs on the die? or do fault/error injections in one of the dies?
Just wanted to understand what is the level of depth we go in for testing after fabrication.
P.S.: My question maybe very basic as I am a SoC Verification Engineer on the frontend side and I am not aware of all the backend testing and intricacies.

[@malashis]

Nice

[@RaspyYeti]

5.5D design is ideal for stacking a CPU/ML die with a GPU die then having a IO/Memory die to the side
Has anyone tried a punch card sale die design that lines up holes subject to thier compass direction?

[@arslansattar351]

its work jumping curent