FPGA FM Modulator with DDS

This is video I'm describing how to use the DDS (Direct Digital Synthesis) as a frequency modulator by changing the phase increment. The video is presenting the principle of DDS and different tradeoffs A Vivado example can be downloaded as an example and the presentation used in video as well. Quality of video is not great I hope the information will compensate for that.
Enjoy!
design files can downloaded from my Blog page
www.adaptivede...

[@benish0r]

Very informative, I learned a lot. Thank you!

[@adaptivedesign8795]

Glad it was helpful!

[@arpit4681]

Thanks ..for this informative video..

[@adaptivedesign8795]

Great! Thanks for watching.

[@Amirhossein_1996]

Hi Mr. How can i send modulated signal from fpga to receiver? Does DDS can send that?

[@manuelsanchez1262]

Hello. So would the adder be the equivalent of the "phase_inc" block you have in your other videos? I am trying to piece the whole radio together (i.e., the final block diagram of the radio) but this doesn't exactly go over the phase_inc block. Instead of audio like you do here, we would be passing in the 16bits from the dc_off_remove block to the adder right? Also, on the phase_inc block, you have two clocks, aclk and dds_clk, why is this?

[@justotalkalottashit8392]

I have a custom ka-band direct digital synthesizer from NASA, that i bought at a surplus sale. Wondering what to do with it as it is missing one part, has these 3 brass colored modules inside of it labeled 75mhz and one is missing.

[@adaptivedesign8795]

I seriously don't know what to say...

[@fc3fc354]

Hey guys,
Sorry for the question it's only a little bit related to the video.
For implementing a Hamming Window on some signal (that will be inputted sequentially) should i just store the hamming coeff. In ROM and multiplu to the input or calculate coefficients dynamically with DDS giving us the coefficient value
Or We would use Dynamic calculation only when we do not know the value of the input size

[@adaptivedesign8795]

you have a few choices (nothing to do with the DDS) you can pre-compute your hamming scaling coef (or any other window function) store them in RAM and multiply them with your incoming samples as they come. I would do this a AXI stream IP core which can be configured for different lengths and different type of windowing. (or configurable on the fly if necessary)
Have fun!

[@fc3fc354]

@@adaptivedesign8795 thanks a lot
You are being a very good support to the FPGA community 😄

[@samjef8131]

perfect. thanks a lot

[@bob_mosavo]

Thanks 👍

[@adaptivedesign8795]

Welcome 👍