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Adaptive Design
Ireland
เข้าร่วมเมื่อ 4 มี.ค. 2016
This Channel is about Electronics, Engineering, Manufacturing and is covering many aspects from PCB design, FPGA Design, PCB assembly, C Programming and many aspects to of modern electronics.
FPGA FM Modulator with DDS
This is video I'm describing how to use the DDS (Direct Digital Synthesis) as a frequency modulator by changing the phase increment. The video is presenting the principle of DDS and different tradeoffs A Vivado example can be downloaded as an example and the presentation used in video as well. Quality of video is not great I hope the information will compensate for that.
Enjoy!
design files can downloaded from my Blog page
www.adaptivedesign.ie/blog
Enjoy!
design files can downloaded from my Blog page
www.adaptivedesign.ie/blog
มุมมอง: 481
วีดีโอ
Using FPGA in radios
มุมมอง 1.8K2 หลายเดือนก่อน
Compared with analog signal processing technology, DSP has the advantages of accurate signal processing, the capability of strong anti-interference, high speed in long-distance transmission, and low distortion. In this video I'm enumerating some of the advantages of using FPGAs (DSP techniques) as I see them from my angle. Feel free to drop comments. Some related videos about FIR filters and Cr...
HW Engineer as a career path
มุมมอง 5083 หลายเดือนก่อน
In this video I'm describing different types of hardware engineers (Electronics) - and some advices which might lead you to choose this as a career path
FPGA DAC testing
มุมมอง 8184 หลายเดือนก่อน
Video where I'm showing the testing of DAC on the FPGA ADC-DAC board. I made many mistakes, wrong assumptions and compromises but in the end it all worked out. Enjoy!
How fast your FPGA will go?
มุมมอง 1.3K4 หลายเดือนก่อน
In this video I'm benchmarking a 32 bit counter on a ZYNQ (Artix) FPGA and achieving 350MHz trough a few iterations. It's a fairly long video so brace yourself but many things to learn from it (I hope) Enjoy!
PCB CLK line Overshoot fix
มุมมอง 2485 หลายเดือนก่อน
This is video where I'm describing a real problem which led to a EMC test failure. The culprit was a mismatch between the CLK driver and PCB impedance. I simulated the problem in LTSpice with some degree of accuracy (I hope) - and described the fix. Please watch in 1080p resolution otherwise the graphs are impossible to see. Enjoy watching!
FPGA DSP FIR filters coefficients
มุมมอง 2.4K5 หลายเดือนก่อน
In this video I'm presenting a tool to design filters and calculate the coefficients. This tool was designed by Dr. A R Collins who was very kind to let me use it for my video. After getting the coefficients I'm plugging them into the Xilinx/AMD FPGA tools as quick demo I hope you enjoy the video! Here is the link to the tool www.arc.id.au/FilterDesign.html Have fun
FPGA Quick-and-Dirty Logarithms
มุมมอง 8727 หลายเดือนก่อน
In this video I'm describing a method to calculate the Log value in dB from a linear value. This block is used to display signals on the logarithmic scale on spectrum analyzers for instance where small signals have to be displayed next to strong signals. The method is described on the DSP Guru website but I come up with a very fast implementation which is different from the suggested one. dspgu...
Required Skills to learn FPGA
มุมมอง 5K7 หลายเดือนก่อน
In this video I'm enumerating and elaborating on the skills you should have before starting to learn how to use FPGAs. This is just my view after 24 years of using them. I might be wrong if you feel that I need to be corrected or I missed anything important please drop me line in the comments. Enjoy!
PCB Fiducials
มุมมอง 5117 หลายเดือนก่อน
This is a video about PCB fiducials, what ? why? and where should be located on the board. This information is not covered in schools (maybe it is in some) and most rookie designers have no idea about fiducials. I hope this info it helps the youngsters to become better designers. Have fun and keep building useful stuff!
Testing The ADC on the ADC DAC FPGA board
มุมมอง 2.1K8 หลายเดือนก่อน
In this video I'm showing the process of testing the ADC interface of my ADC DAC FPGA board using some fixed patterns generated by the ADC chip and later on sampling a sinus signal from the signal generator. All working but I had to correct some mistakes that I made along the way (bit swap in the DDR capture registers) and data inversions (the usual stuff) all took half a day. The ADC registers...
The Build ADC DAC board for FPGA
มุมมอง 1.3K8 หลายเดือนก่อน
This series of videos are about a Hobby project which I'm working on, is a over the average hobby level but still achievable by many of us. The main idea is build a board that I can attach to my FPGA board (Zedboard) for sampling radio signals and synthesizing signals too. Episode 2 is just an update of the buid Enjoy the video!
The Making of an ADC DAC board for FPGA
มุมมอง 3.2K9 หลายเดือนก่อน
This series of videos are about a Hobby project which I'm working on, is a over the average hobby level but still achievable by many of us. The main idea is build a board that I can attach to my FPGA board (Zedboard) for sampling radio signals and synthesizing signals too. The ADC has a sample rate of 80Mhz (125Msamples ADC are available footprint compatible) and a resolution of 14 Bits. The ou...
Visualizing RF signal from inside the FPGA
มุมมอง 8599 หลายเดือนก่อน
In this video is presented an idea on how to visualize in frequency domain and real time a signal from inside of the FPGA on an external monitor, like built in crude spectrum analyzer which resides next to your main design. This is part of a bigger project (hobby) for building a digital radio on the FPGA, and will become a tool to test my new ADC-DAC 14 board which is in the making video link b...
VGA 640x480 Timing Generator in VHDL and a Test Bench with ChatGPT
มุมมอง 7269 หลายเดือนก่อน
In this video I'm showing how you can generate a timing generator for VGA 640x480 pixels in VHDL. The code generated is 100% usable and a Test Bench was generated too. The code is plugged (copy paste) into Vivado and simulated with no major issues. Please let me know in the comment if you want to see the code implemented on Hardware. This video was done in one go (no editing) so don't expect to...
Running an Electronics Manufacturing business in Ireland part 1
มุมมอง 3.4K2 ปีที่แล้ว
Running an Electronics Manufacturing business in Ireland part 1
Very good video helped a lot;)
I'm glad you like it!
Thank you for a wealth of knowledge. AMD marketing heavily emphasizes the numbers in Versal - 2.2 GHz and 1.05 for HPS, and around 1GHz on the PL side of things. How realistic is that and is this possible mostly because of the physics at that process ? (tsmc 7nm)?
Versal is a modern FPGA fabricated on a much smaller node the one I'm presenting there is 2010-2012 generation so Versal it might well be that fast (life taught me to water down a bit the marketing claims) - I don't think AMD is making false claims but probably on the high side. I might repeat this video with a Versal when I get my hands on one. Thanks for your appreciations,
thank you
you're welcome, I'm glad you liked it!
Awesome channel, great video. Do tell me, why are salaries in hardware about the half compared to software for three times the mental effort ?
Just my opinion (may differ from the truth) the software as a business model is more attractive to the investors because it can be scaled up very quickly, in turn these companies are flooded with investment money (easy money) and they pay big salaries. (most of these companies they don't even make profit) - In well established companies software salaries are not exceeding hardware salaries (or are less) - another reason is that manufacturing (and designing) hardware has migrated offshore and is perceived as a risk by most of the company leaders which are not engineers. Life has a habit to balance these things naturally but it can take a long time.
@@adaptivedesign8795 I guess you’re right - there is very little correlation between actual depth and breadth of skillset in software to the size of compensation. I started looking into hardware when I realized that the stereotype that outside world has about hardware - that “some guys” are always gonna be there to do it for the bottom dollar like it’s a roofing job (no offense to roofers) - anyway, it’s false and damaging. I found the little bit of relevant hardware design I could scrape with my meager knowledge to be at least as challenging and dependent on fundamentals as the mid level systems development - stuff like storage optimization for database or simpler drivers design. There isn’t enough respect for people on whose shoulders everything stands - literally every aspect of our society is on backs of people who took some serious gambles with their lives and very few of them got rich quick doing so. BTW you forgot the most important skill in FPGA : written mandarin :-)
@@unixux nobody is getting rich quick in engineering, not sure about learning mandarin either, learning Verilog/VHDL it's a much safer bet.
Sorry I have a question , i understand the decimation process and the use of cic for anti aliasing , but i dont understand how come are the pdm encoding transformed into pcm , since we don't have neither info about bit depth of the pdm signal but just the clock signal
Hi There, The pdm output is one bit but on each stage of decimating and low pass filtering (inside the stages of CIC filter) you'll have a bit growth so you end up will a much slower (sampling rate) signal but much wider. The "secret" of the PDM signal is that it contains you audio signal in a very fast digital (noisy) signal with the property of all the noise being located at higher frequency, By decimating and low pass filtering we get rid of the noisy part and remain with the audio component (or band).
@@adaptivedesign8795 thanks for your response so basically if I have a 3 Mhz PDM signal and if i want to have a 8 bit pcm as output , theoretically would be like waiting for 2^8-1 pulses of pdm and in base of the ratio of 1s over total length the pcm data would be defined so if my deduction is correct For 1/3Mhz * 256 would be considered the signal for 1 sample so the pcm sampling would be 1/3Mhz *256?
@@fc3fc354 That's a very simplistic way of describing it, the bitstream is getting decimated by a large factor 256 (if my memory serves me right) but every time you decimate you need to low pass filter the signal, hence the use of CIC which is perfect for this application because of the large decimation ratio. However nothing will stop you counting the number of 1s and 0s over a 256 bit window and slide that window. if the number of 1s and zeros is the same that's 0V,. if all bits are 1 that's your positive max if no 1s (all are zeros) that's your negative max. My guess is that you'll still need to low pass your new signal for the audio band. this could be an idea for new implementation.😀 your new sampling rate will be the original / 256 (so every 256bit in the PDM stream you'll have one PCM sample)
Pretty nifty trick, great for waterfalls and agcs :) Thanks!
perfect. thanks a lot
Hello. In the pdm_axi block, you are outputting 8bits on the tdata axi signal. But you say the pdm microphone sends 1 bit bitstreams. So are you waiting 8 clk cycles (at 3.072mhz) to capture 8 bits of pdm data before you send out tdata? Also, in the CIC, you set your input data width to 2, but you are sending 8 bits, why is it only 2? Thank you in advance.
Hi Manuel, I'll start with the CIC - the input of the CIC has a minimum of 2 bits (width of data) because is taking signed samples (on two bits you have the range from -2..+1) so you have map the output from the microphone 1 and 0 to values to values of -1 and +1 in order to be compatible with the CIC (exactly in the same way you can map them to 8 bit to actual values of -127/+127) because AXI interface works in chunks of 8 bits. (btw when you use values lower that 8 bit chunks on AXI you need to make sure you sign extend your values) The remapping mechanism from 1 and 0 to 8bit signed (-127/+127) does both ie. converting unsigned 1 bit samples into 8 bit signed values (two complement format) this can be done with a mux (in VHDL/Verilog) Let me know if you got it. A
@@adaptivedesign8795 Yes thank you! That cleared up my confusion.
@@adaptivedesign8795 I also wanted to ask if you can give an overview of what the phase_inc block that you have does and how you implemented it so I can do that in verilog. This is the block that sets the phase increment of the dds compiler, I see it in your block diagram in the video where you show the 144mhz transmitter. Thank you.
Hello. So would the adder be the equivalent of the "phase_inc" block you have in your other videos? I am trying to piece the whole radio together (i.e., the final block diagram of the radio) but this doesn't exactly go over the phase_inc block. Instead of audio like you do here, we would be passing in the 16bits from the dc_off_remove block to the adder right? Also, on the phase_inc block, you have two clocks, aclk and dds_clk, why is this?
Sir, how can i get a job if companies asking 4,5 years of experience? Do i need to make projects ? I dont have work experience
Making your own projects (not replicating) is always the best way to learn. Work somewhere else (not necessarily in a FPGA position) ideally digital, and keep building expertise. Another way is to be franc with the employer and tell them you don't have 4,5 years you have only X but you are willing to learn, you never know maybe they have a junior position they never advertised. Good luck!
@@adaptivedesign8795 thanks for the reply. I live in the U.S. and over here very few jobs avaialble in the electronics/hardware field. I have 5+ years of expereince working in the software development field, worked on Object orirented programming. I belive I can transfer my coding skills and other skills like Git, Agile methodology, Bug fixing etc.? If I have projects like SPI,I2C, VGA, Ethernet , will company consider it as experience? I can explain it in the interview. Thanks
I have a custom ka-band direct digital synthesizer from NASA, that i bought at a surplus sale. Wondering what to do with it as it is missing one part, has these 3 brass colored modules inside of it labeled 75mhz and one is missing.
I seriously don't know what to say...
Thanks 👍
Welcome 👍
Thanks 👍
Welcome 👍
Very informative, I learned a lot. Thank you!
Glad it was helpful!
please explain more about changing phase increment in dds. with which rate we should change phase increment of dds?
I added a new video which elaborates a bit more (I hope) th-cam.com/video/7XSGRYAp7xs/w-d-xo.html
@@adaptivedesign8795 thank you very much
Hello, the videos you have give a good general overview of how the fpga radio works. But where could we find the code for the modules we need to get this working as well as a nice video that shows the entire block diagram of the radio working together? I feel like this video shows a part of the radio, but not all of it as a whole so it's hard to piece everything together. Thanks!
Statistically people watch about 2 minutes from a 10 minute video (I guess they are kinda crap and in a weird accent, thanks god we have auto generated captions) - Talking about building a whole radio will take to long so I tried to break down the subject in multiple videos, I'll do my best in the future to strike a better balance. Thanks for your feedback.
I'm trying to use my on board pdm mic to recieve music notes from a guitar and recognize them. I have a cic filter from the ip catalog I'm using. Its the same decimator filter, very similar to the one you showed in your other video where you were explaining how to get that external mic going. I don't think the filter is giving anything useful. Can you recommend a filter or series of filters I should try to implement that would recognize and distinguish the guitar string notes between 100 Hz and 1000 Hz? Thanks if you have any ideas.
I'm thinking to make a tutorial A to Z about this subject including how you debug it.
Your accent sounds romanian, I don't know why. Thank you for the nice video!
Salut Adrian, sunt nascut in Romania stabilit in IRL.
@@adaptivedesign8795 Salut! Ma bucur ca nu m-a inselat urechea :) E fascinant topicul FPGA-urilor pentru radio. Tot incerc sa intru in lumea FPGA-urilor insa e destul de greut pe cont propriu. Lucrez la un transceiver SDR care functioneaza momentan cu MCU-uri din familia STM32F(H)7 insa as dori sa trec la FPGA din motive de performanta. Crezi ca te-as putea contacta pentru niste sfaturi? 73 de YO6SSW
@@adaptivedesign8795 Salut! E fascinanta lumea FPGA-urilor. Incerc sa acced la ea de ceva timp insa e mai greu de unul singur. Lucrez la un radio SDR de ceva timp si as dori sa migrez parti care acum ruleaza in MCU pe un FPGA. Crezi ca te-as putea contacta pentru sfaturi/discutii? Multumesc, Adrian YO6SSW
Aparent YT face tot soiul de chestii dubioase si nu-mi posteaza reply-urile la reply-uri :-) Unde te-as putea contacta pentru sfaturi legate de FPGA? 73 de Adrian YO6SSW
Daca ai linked-in cauta-ma Aurelian Lazarut 73 de EI3HWB
if i don't want to use fir ip than how can i convert cofficient into hexadecimal and write into my code. if possible please make a detail video in this or please provide some brief about this in comment
you can use excel, lets say you want to convert them in 16bit values (signed) 1. the copy the values from the website in a column in excel (spreadsheet) - the values are from -1 to 1 (actually -0.9999 to +0.9999) 2. Multiply each value with 32767 (maximum of a signed 16 bit number) - this will result in values from -32767 to +32767 3. Convert into integer 4. Convert into hex values you can achieve the same thing with script in python or any other language program. Let me me know if this sufficient to get you going.
perfect. thanks
You're welcome!
PERFECT🤩🤩🤩
Three smilies! PERFECT indeed
Hello. I want to try to replicate this using my iphone as an audio source. Could you show what the block diagram is and how to configure it? Also what do you connect to the board to provide audio from the iphone? And if we have a board that has a DAC, we could just use that correct? I have vivado so I plan to use that as well.
I used a codec chip (it was in my board - Zedboard) and on the manufacturer website I think they have an example in VHDL - that was my way but it depends what you have on your board.
Thanks 👍
I'm glad you liked it!
Hello! I thought about full digital radios - there must be an excellent ADC: to avoid intermodulation distortion and noise.Maybe down-sampling helps to avoid extremely expensive 16bit ADC 60MSPS. My history about program logic was sad. I know the C language, microcontrollers , analog RF electronics. Several years ago I tried to write some software for FPGA. It was a simple serial interface for external ADC and DAC and a simple bass filter. It takes several days (I had done it) - but I was there so exhausted that I had a sleepless night... As a result I sold my FPGA Altera developer board.
Andrew, I think you are made from the right material, I had many of those ups/downs. For audio applications FPGAs are overkill but for high sample rates and more complicated stuff are working like a charm. I hope you get back to it someday. Take it Easy!
20 minutes of talk with absolute no value lol
I agree, no cats in it, no crypto, no drama. I feel you man.
@@adaptivedesign8795stop making videos lol. maybe you can watch some videos on how to talk less but it contains everything
what videos ? I have only one.
@@adaptivedesign8795 don’t giver users trauma ok ?
very helpful
Glad to hear that, I didn't expect many watchers to be honest.
keep it up, very cool!!
Thanks, will do!
Do you work for a company that assembles PCBs? If so, can you provide a name/website please?
Adaptive Design ltd. (Ireland)
Great informations
Glad it was helpful!
73's AP2SM
Glad you like it! more to come ab out digital radios (not SDR) 73's EI3HWB
Learning vlsi is easy but master is very hard.
if it was easy the world would full of experts.
Sir can you add this project's specific files of vivado block level coding on your website or maybe make a video for modelling this please. I'm working on a similar project.
Hi There, I'll try to add more code on my blog page in the future, I have more videos to come Thanks for watching!
Great topic. Water cooler stuff. Might be good to discuss the FPGA enginner career path which is often launched from a hardware background.
It has to be from hardware, I didn't see any FPGA engineer coming from a software background (maybe they are out there but I didn't come across one)
Have been seeing new grads that come from 'computer engineering' majors which are about 1/2 EE & 1/2 CS
I take that as good news!
Thanks for this video sir I'm a final year student of electronics and pretty much confused about the paths Again thanks for the clarification 🎉
You are most welcome, keep up the good work!
Fantastic video, I agree with everything you said! 👏
Awesome! Thank you!
Ireland is corrupt
it's not corrupt as a country I think the politicians are completely disconnected from the citizens
Hello! I very much found your video amusing because I was also struggling with an Analog Devices DAC this week turns out my JESD204 lane mapping was off... I have a matter I would like to hear your opinion on: What would you like to see in a portfolio of a FPGA Engineer with 4 years of experience? Specifically one that specializes in RF and DSP implementations.
Hi Ronald, I was actually planning a video about the subject but here we go: making a carrier in FPGA design (design services) can be achieved in two ways as an employee or as free lancer. Both paths are difficult but rewarding Employers like enthusiastic people, self learners and creative people. (I might sound like captain obvious but that's the truth) - Making a useful project is a good way to show off and might impress some potential employers. Just a piece of advice, general knowledge of electronics is key, focusing on just FPGAs can be limiting sometimes (to narrow specialized) you might find a good employer but you might get stuck there for long time. I think the key aspect is to keep learning you are on the right track.
@@adaptivedesign8795 Thank you for answering! Looking forward to your video on the topic!
Love this project. I'm building an FPGA based SDR as well! Perhaps we can work together? Make a radio to rule them all!!!
Glenn, I'm still miles away from that but getting there...
@@adaptivedesign8795 haha, I never said it was easy! Real engineering is not for the faint of heart :)
very interesting
Glad you think so!
Very informative. Thank you for the video!
My pleasure!
Good job !
Grad you like it!
Love this content, keep it up! I have shared your channel with my business page on LinkedIn by the way :) P.S. I particularly like that you explain all the acronyms and assumptions in this video as you go, this makes the barrier to entry much lower allowing students to watch along which I'm certain they will appreciate a lot!!
Much appreciated!
Glenn, I hope I'm not going to fail that often...
This is a fantastic video, I would love to see more videos about solving EMC test failures!!
More to come!
@@adaptivedesign8795 fantastic!!
Nice website for the filter design, I haven't come across that one before!
Glad you like it!
@@adaptivedesign8795, please keep it up, we need more of this!
Hi Adaptive design! I love your walkthrough about the making of an high speed adc and I highly appreciate it! I am designing something similar on my own and i would like to know is there a github or something eqivalent where we can have a look on your hardware/vdhl implementation in vivado? I am looking forward to hear from you. Best regards. Natrox
Hi Natrox, I'll add the Vivado project on my Blog page but I'll warn you in advance is not much in there and is very specific to the board I built. (just a bunch of DDR input registers and an ILA to capture the singals) Aurelian
@@adaptivedesign8795 Hi Aurelian! Many thanks! I appreciate your effort and your contributions!
Added on the Blog page - link in the description Have Fun!
@@adaptivedesign8795 Thank you very much! have a great day!
Thank You Sir for sharing your experience!
I might have sounded grumpy in that video, in reality running such a business has a lot of positive moments and satisfaction, if you like what you are doing. Happy to share some more in the future. Have fun!
Very nice video! Nicely done. I wonder how did you derive that the problem was with the DDR?
Hi There, I figure out the DDR problem by looking to the captured signals using the ILA (integrated logic analyzer) if you sample a sinus signal you can see how the samples are crossing zero and they change the sign (twos complement) and it becomes obvious. With a checker board test signals you can't spot these type of errors
Hello Adaptive Design, hope my message find you well. i would like to have your xdc file as i would like to use it as a template for a project where i use an adc. Thank you and have a nice day.
Hi There, sure no problem I can give you the xdc please go on our website on the contact page and fill in the form (by doing so I'll get you email whithout exposing it here) www.adaptivedeisng.ie contacts subpage. After having your email I can send you file as an attachment. Have fun, A
I added in the video description a link to my blog where you can find a the XDC file and schematics
@@adaptivedesign8795 Hey thanks for answer. I tried to open the link but it's not work. "safari can't open the server."
@berukchimi6947 www.adaptivedesign.ie/post/adc-dac-board-for-fpga-zed-board just tried and working with chrome/firefox/edge on PC and safari from my Iphone
Genious, love the simple and quick explanation. Keep it up!
Glad you liked it! more to come.