Cadence Virtuoso: Optimization of PMOS Width in ADE Assembler.

This video show the process used for the optimization of PMOS width of simple CMOS Inverter using ADE Assembler in Cadence.

[@SRIHARSHABHATTU]

Thanks for videos

[@dr.hariprasadnaikbhattu]

Welcome

[@akshaybhargav1086]

Sir even after attaching the mode files I'm facing an issue in the simulation of ADE Assembler. Does the assembler works in the cracked version of Cadence

[@dr.hariprasadnaikbhattu]

Yes, it works. What is the check it in Google once.

[@rahulbhattu7661]

Thank you

[@dr.hariprasadnaikbhattu]

You're welcome

[@vermatushant]

unable to edit length and width in the nmos cadence virtuoso 45m library? please help

[@dr.hariprasadnaikbhattu]

Hi any given gpdk is editable. I didnot come across such issue. If length and width scaling has lower and upper limits.

[@ardalankhodadadi4726]

Hi sir my question is irelevant about this video but I have question
I'm using delay function to calculate tpdf and tpdr of an inverter but the value of two this is wrong value when I saw graph and use horizental line for calculate tpdr and tpdf it's OK and correct value but I use calculator It's wrong and I should have these to tpdr and tpdf value in my outputs can you tell me what's wrong with this please thanks

[@dr.hariprasadnaikbhattu]

Use this video link
th-cam.com/video/6SwIVwXL4t0/w-d-xo.html

[@kolaveri70]

Thanks

[@dr.hariprasadnaikbhattu]

Welcome

[@rahulbhattu7661]

Thanks

[@dr.hariprasadnaikbhattu]

You are Welcome

[@rahulbhattu7661]

Thanks

[@dr.hariprasadnaikbhattu]

Thanks