Hey everyone, we filmed a 2nd video on this topic where we talk about some strategies for improving the layout. It should come out in a few days, I'll post the link here when it's ready!
Dear Zach. I found a few issues with both single and dual layer designs you showed us. 1. The FB trace must be as short as possible. As you said, it's a high impedance trace. Both FB resistors must be as close as possible to the IC's pin. The long trace has to be the +Vout. Not the FB trace. 2. Try to avoid components and any traces under the inductor. Usually, I add a keep-out square for both the top and bottom layers, isolating the GND plane under the inductor. 3. Try to make the SW noisy track as short as possible by moving the IC as close as possible to the inductor. Also, the boost capacitor must be close to the inductor too. Best Regards
We actually filmed a part 2 to this already where we talk about some of these points so that we can make the layout more compact and deal with the points you mentioned. Just a simple 90 degree rotation on the SW regulator chip helps with this alot. Also the FB pin is a high impedance input, but that is not the problem, the issue is the length of the trace and the possibility for it to receive noise, both due to its length. Stay tuned for part 2!
The input capacitors current path is important as well. When the high side mosfet is open, the high di/dt path includes input and output caps, inductor and high side mosfet. In two side version of your layout the input capacitor ground path to output capacitor is very long and narrow.
Yeah that's a good point, in the 2nd video we did some component shifts to get the layout more compact, it ends up putting the input caps closer to the 12V pin with just a 90 degree rotation on the regulator chip.
Hi Zach - thanks for the video. But I wouldn't route the feedback trace under the switching node on a 2 layer board. Also of interest would be the polygon arrangement for a switcher on a 4-layer board - is plane GND on layers 2 and 3 under the switcher the best approach?
Yes putting GND on L2 would be a good practice once the board gets dense, although I've always seen a bit of controversy about it you would do this if you were going to support some high speed components. You'll notice along the bottom of the screen that the board has 4 available layers, we're just looking at using two of them (top and bottom) for the components and routing.
Hi Zach! About the FB line, why in both cases is there no GND plane under the FB trace? In the 2nd case, the FB trace passes under the switching node without shield (GND) in between. The current return of FB trace is sharing with the current loop introducing cross talk? Thank you!
So in that FB line, it is best to try and keep it away from the SW node. I did this one initially just to show a thought process behind shrinking the overal loop area on the output loop (same principle would apply to the input loop). In the 2nd part of this, I showed a couple strategies to move things around and try to get that feedback trace smaller. Also you'll notice on the screen that this is a 4-layer board, and if you were going to do this regulator on 4 layers then you can put ground on L2, that will shield the feedback line from the SW node. That type of board would also be appropriate if you were going to use the regulator for high-speed components. You can watch part 2 here: th-cam.com/video/5q4on8L1vKo/w-d-xo.html
Hello Zach Sir loved the explanation on how to reduce the loop area and switching noise!.... Shouldn't the feedback resistive network be as small as possible?... as longer feedback traces can couple more noise!
Hey man you're already giving away the topic of one of our next videos! We filmed one about improving the layout so we can deal with noise problems from long coupled traces. It's part of a short series on crosstalk.
Thank you. It is not good idea to follow your options. However, 1-layer board having C1&C2 &C3 & C4 on top is the best. C3 & C4 should be perpendicular to C1& C2 (say upper side of top layer. Current placement of C1 & C2 is OK) with short and direct ground connection is the best solution for the shortest loop between input and output caps thus for the best EMI. Feedback resistors should be located at the lower side of top layer. No need to extend Vout copper pour to the right, instead towards to C1 & C2. This results in decreasing length of the board as well.
Thank you for your awesome video!! Maybe this is a silly question but I don't get why the high current loop is through C3 and C4. I mean DC current does not flow through capacitors... Could you please explain?
It's not DC current, it's a switching current, so when the regulator switches it's drawing AC current into/out of those caps. The DC portion does see high (infinite) impedance across those caps so it would be directed towards the output.
I recently created a PCB roughly based on a Texas Instruments Layout. To my surprise, the P channel MOSFET they used was placed between the inductor and the output capacitors. I thought this was strange, since it would probably not help with noise. Is there a reason they would do this? I figured it would be a better idea to place the P-FET after the output caps.
The answer depends on the topology and the part you are using. This is the kind of thing you might see with a bridge topology that is being used on each side of the inductor, so on that you will have two FETs after the inductor. Those are often N-channel MOSFETs but they could be P-channel. Can't say more without knowing the part number though.
Hey Zach! Thank you for another awesome video! Love to see a video on good practice design rules before layout (unless I miss a video somewhere lol) Also what's your workout routine? 💪 haha
Thank you and Altium for these great videos. Can you or anybody tell me, where those vias are connected, to reduce the di/dt loop? Are they only connected to the ground layer? In 3d view it looks like, they are shorted between ground and power layer.
The vias are not shorting power and ground. They connect to the 5V net on the top layer, and to a 5V polygon on the bottom layer. I understand it might be confusing in the 3D view, but if you hold the Shift key with the mouse hovering over a net in the PCB layout, you will be able to see all the connections to that net.
Thank you so much! It's very helpful! I'd like to know if it's necessary to cutout the copper/polygon under the inductor(multi layer)? Seems it's quite offen to do it. Thank you
Hi Zach, i appreciate this kind of video but honestly i think that positions of R1 and R2 are totally off! The best way is to place them close to FB pin in order to have a small and clean connection.
Hey Luca, glad you noticed and you just pointed out the topic of an upcoming video! Yes that would be a better option as the idea in precision tracking with a DC resistor is to eliminate any resistance from the connecting traces, although sometimes it's tough to do that when you have a big inductor. We filmed another video on improving the regulator to make it more compact so we can get more accurate feedback, it should be up soon!
@@Zachariah-Peterson Good to hear! Another important aspect is to keep the sense of Vout as close as possible to last output cap or near the load as possible. And don't forget the input loop, especially in buck regulator it's really critical! Much more than the output loop... The last thing that I've notice is the placement and layout for bootstrap capacitor... in my experience I've see that the best way to connect it's from boost pin directly to SW pin without sharing track, or region, needed for connect the start winding of the inductor to the sw pin.
@@lucabelvederesi6914 Yeah that cap was a tough compromise the way it is placed just because the package is so small. Rotating 90 degrees does the trick and makes it a lot easier to improve the layout, that's what we did in the other video
can`t see a point of this video, except Altium demonstration, or note that you can place components on both sides. as this design got lot of issues that will strongly degrade performance on input and output. you should`n do that on practice
I can't find a part number with TPS5149, did you mean to write TPS51488? How about a flyback converter with one of the UCC controllers? Those controllers are fun to work with.
Hey everyone, we filmed a 2nd video on this topic where we talk about some strategies for improving the layout. It should come out in a few days, I'll post the link here when it's ready!
Dear Zach. I found a few issues with both single and dual layer designs you showed us.
1. The FB trace must be as short as possible. As you said, it's a high impedance trace. Both FB resistors must be as close as possible to the IC's pin. The long trace has to be the +Vout. Not the FB trace.
2. Try to avoid components and any traces under the inductor. Usually, I add a keep-out square for both the top and bottom layers, isolating the GND plane under the inductor.
3. Try to make the SW noisy track as short as possible by moving the IC as close as possible to the inductor. Also, the boost capacitor must be close to the inductor too.
Best Regards
We actually filmed a part 2 to this already where we talk about some of these points so that we can make the layout more compact and deal with the points you mentioned. Just a simple 90 degree rotation on the SW regulator chip helps with this alot. Also the FB pin is a high impedance input, but that is not the problem, the issue is the length of the trace and the possibility for it to receive noise, both due to its length. Stay tuned for part 2!
The input capacitors current path is important as well. When the high side mosfet is open, the high di/dt path includes input and output caps, inductor and high side mosfet. In two side version of your layout the input capacitor ground path to output capacitor is very long and narrow.
Yeah that's a good point, in the 2nd video we did some component shifts to get the layout more compact, it ends up putting the input caps closer to the 12V pin with just a 90 degree rotation on the regulator chip.
Hi Zach - thanks for the video. But I wouldn't route the feedback trace under the switching node on a 2 layer board. Also of interest would be the polygon arrangement for a switcher on a 4-layer board - is plane GND on layers 2 and 3 under the switcher the best approach?
Yes putting GND on L2 would be a good practice once the board gets dense, although I've always seen a bit of controversy about it you would do this if you were going to support some high speed components. You'll notice along the bottom of the screen that the board has 4 available layers, we're just looking at using two of them (top and bottom) for the components and routing.
Hi Zach! About the FB line, why in both cases is there no GND plane under the FB trace? In the 2nd case, the FB trace passes under the switching node without shield (GND) in between. The current return of FB trace is sharing with the current loop introducing cross talk? Thank you!
So in that FB line, it is best to try and keep it away from the SW node. I did this one initially just to show a thought process behind shrinking the overal loop area on the output loop (same principle would apply to the input loop). In the 2nd part of this, I showed a couple strategies to move things around and try to get that feedback trace smaller. Also you'll notice on the screen that this is a 4-layer board, and if you were going to do this regulator on 4 layers then you can put ground on L2, that will shield the feedback line from the SW node. That type of board would also be appropriate if you were going to use the regulator for high-speed components.
You can watch part 2 here: th-cam.com/video/5q4on8L1vKo/w-d-xo.html
Hello Zach Sir loved the explanation on how to reduce the loop area and switching noise!.... Shouldn't the feedback resistive network be as small as possible?... as longer feedback traces can couple more noise!
Hey man you're already giving away the topic of one of our next videos! We filmed one about improving the layout so we can deal with noise problems from long coupled traces. It's part of a short series on crosstalk.
THANK YOU SOOOOO MUCH, DR. PETERSON!
This was very very good...thanks Altium academy
So nice of you
very good and useful, thank you very much
So nice of you
Thank you. It is not good idea to follow your options. However, 1-layer board having C1&C2 &C3 & C4 on top is the best. C3 & C4 should be perpendicular to C1& C2 (say upper side of top layer. Current placement of C1 & C2 is OK) with short and direct ground connection is the best solution for the shortest loop between input and output caps thus for the best EMI. Feedback resistors should be located at the lower side of top layer. No need to extend Vout copper pour to the right, instead towards to C1 & C2. This results in decreasing length of the board as well.
Thank you for your awesome video!! Maybe this is a silly question but I don't get why the high current loop is through C3 and C4. I mean DC current does not flow through capacitors... Could you please explain?
It's not DC current, it's a switching current, so when the regulator switches it's drawing AC current into/out of those caps. The DC portion does see high (infinite) impedance across those caps so it would be directed towards the output.
I recently created a PCB roughly based on a Texas Instruments Layout. To my surprise, the P channel MOSFET they used was placed between the inductor and the output capacitors. I thought this was strange, since it would probably not help with noise. Is there a reason they would do this? I figured it would be a better idea to place the P-FET after the output caps.
The answer depends on the topology and the part you are using. This is the kind of thing you might see with a bridge topology that is being used on each side of the inductor, so on that you will have two FETs after the inductor. Those are often N-channel MOSFETs but they could be P-channel. Can't say more without knowing the part number though.
Hey Zach! Thank you for another awesome video! Love to see a video on good practice design rules before layout (unless I miss a video somewhere lol)
Also what's your workout routine? 💪 haha
Thank you and Altium for these great videos. Can you or anybody tell me, where those vias are connected, to reduce the di/dt loop?
Are they only connected to the ground layer? In 3d view it looks like, they are shorted between ground and power layer.
The vias are not shorting power and ground. They connect to the 5V net on the top layer, and to a 5V polygon on the bottom layer. I understand it might be confusing in the 3D view, but if you hold the Shift key with the mouse hovering over a net in the PCB layout, you will be able to see all the connections to that net.
@@Zachariah-Peterson
Thank you very much.
Thank you so much! It's very helpful! I'd like to know if it's necessary to cutout the copper/polygon under the inductor(multi layer)? Seems it's quite offen to do it. Thank you
That's a great question because it always seems a controversial topic, I'll make a video about it
Can't wait for it! Thank you
Hi Zach, i appreciate this kind of video but honestly i think that positions of R1 and R2 are totally off! The best way is to place them close to FB pin in order to have a small and clean connection.
Hey Luca, glad you noticed and you just pointed out the topic of an upcoming video! Yes that would be a better option as the idea in precision tracking with a DC resistor is to eliminate any resistance from the connecting traces, although sometimes it's tough to do that when you have a big inductor. We filmed another video on improving the regulator to make it more compact so we can get more accurate feedback, it should be up soon!
@@Zachariah-Peterson Good to hear! Another important aspect is to keep the sense of Vout as close as possible to last output cap or near the load as possible. And don't forget the input loop, especially in buck regulator it's really critical! Much more than the output loop... The last thing that I've notice is the placement and layout for bootstrap capacitor... in my experience I've see that the best way to connect it's from boost pin directly to SW pin without sharing track, or region, needed for connect the start winding of the inductor to the sw pin.
@@lucabelvederesi6914 Yeah that cap was a tough compromise the way it is placed just because the package is so small. Rotating 90 degrees does the trick and makes it a lot easier to improve the layout, that's what we did in the other video
Watch Part 2 here: th-cam.com/video/5q4on8L1vKo/w-d-xo.html
My fabricator is getting quite annoyed with me by now... ;)
Thanks
Welcome
I'm ringing my fabricator right now, and he's asking what do I want? I need step 2 to progress
LOL
can`t see a point of this video, except Altium demonstration, or note that you can place components on both sides. as this design got lot of issues that will strongly degrade performance on input and output. you should`n do that on practice
It's too easy. Tell us about voltage regulators using the example of at least tps5149, or even better uc1825
I can't find a part number with TPS5149, did you mean to write TPS51488? How about a flyback converter with one of the UCC controllers? Those controllers are fun to work with.
@@Zachariah-Peterson Sorry, I made a typo. LM25149