Thank you. Trying to learn VHDL and your example was very well presented and most helpful. I have a lot of processor experience and finding it hard to create process flows on an FPGA but I will keep trying.
Dear Steven, thank you for your educative video. I have a short question : usually, we hear that we need to convert an FSM into D-Flip Flops (to implement them in FPGA, this might be wrong part!), but here it seems you are very comfortably expressing it directly as an FSM. Where/when are the D-Flip Flops needed?
Right, it's almost always easier (and often more efficient) to express the FSM directly in VHDL/Verilog, rather than trying to work it all the way down to DFFs and gates. The synthesis tools will happily do that work for you, and because the computer can rapidly search a large number of possible implementations, it may even find a better solution than you would find by hand. Obviously an FSM will still be implemented with flop-flops at the hardware level, but there's generally no need to instantiate them directly.
Ah, the cool thing about this method is that you don't have to specify the mapping of states to bits; the synthesis tool can do that for you. And because it can try a large number of possibilities very quickly, it can (hopefully) find a state encoding that minimizes the number of gates used, or makes the circuit run fast.
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Thank you. Trying to learn VHDL and your example was very well presented and most helpful. I have a lot of processor experience and finding it hard to create process flows on an FPGA but I will keep trying.
Hi, how would you go back from Open state to Idle state. It doesn’t specify what the output is equal to (B or Y) to go back to Idle.
Dear Steven, thank you for your educative video. I have a short question : usually, we hear that we need to convert an FSM into D-Flip Flops (to implement them in FPGA, this might be wrong part!), but here it seems you are very comfortably expressing it directly as an FSM. Where/when are the D-Flip Flops needed?
Right, it's almost always easier (and often more efficient) to express the FSM directly in VHDL/Verilog, rather than trying to work it all the way down to DFFs and gates. The synthesis tools will happily do that work for you, and because the computer can rapidly search a large number of possible implementations, it may even find a better solution than you would find by hand.
Obviously an FSM will still be implemented with flop-flops at the hardware level, but there's generally no need to instantiate them directly.
@@botsnlinux Thank you so much Steven, this nailed it. Keep up your videos!
this response made me subscribe to your channel very clear and helpful@@botsnlinux
Don't we have to initialize the states?
I meant not initializing but define them, like how does the program know that an idle state represents a 00
Ah, the cool thing about this method is that you don't have to specify the mapping of states to bits; the synthesis tool can do that for you. And because it can try a large number of possibilities very quickly, it can (hopefully) find a state encoding that minimizes the number of gates used, or makes the circuit run fast.