The very BEST video I've seen so far on how a PLL might work to increase clock frequencies (e.g. inside a FPGA). It isn't bogged down with implementation details, just the top-level concepts. This makes a lot more sense now. You take an input clock frequency (F) and the output frequence will be (F/M)*N, where M and N are integers.
I am really glad you liked the video. I know from my own experience like to start with a top level explanation and then dive down when I understand the basic concepts. Thanks.
Wow amazing. I just needed to learn how PLL works for work but I don't want to spend days learning about the nitty gritty about it. This is the perfect video. Easy to understand and short. Thank you.
Excellent explanation, yet almost all the information from engineers are basic blocks and superficial reference to the complicated mathematics of the programing of the PLL chip. I have some PLL chips, I need to learn to access and get to run, there isn't any application note for them. Well, the data sheets have basic information for qualified and experienced engineers in the field. But some elaborate examples from talented tutors to newbies, hobbyists, nonexperts would be a hit. Something like setting the chip to default, load with parameters and save a frequency and most important how to extend and expand from this outset. Bringing a PLL chip like the SN761672 or TSA5511 or any other and showing things on the oscilloscope along with frequency counter and a receiver etc.
I confess that I always found the data sheets were a bit lacking. They were of the ilk of "the magic happens here" and no real explanations of how to design with them.
under competition stress they release the part accompanied with mass commercials than support. I guess giant customers get hotline and support once they experience problems.
The digital dividers used between the Vic and phase detector are normally controlled digitally and this means that the frequency of the synthesizer can be programmed by a processor or other digital control.
@@ElectronicsNotes I've been looking at FPGAs, and I see there are templates ("IP") for making PLL circuits in them. I'm now wondering how they make the loop filter, since it's effectively all logic gates. Do they get to skip that part? I guess the VCO has to be numerically controlled too, not a VCO - presumably just a programmable counter / divider.
@@TooSlowTube I confess that I have never designed a synthesizer using an FPGA. My experience has been designing them using more traditional techniques. Interesting project, though. I would suggest a chat with an RF digital designer who has experience with synthesisers. May be the digital elements are covered both e FPGA and the remainder by analogue circuits.
Could you please explain the ending where the divider range is said to vary from 11520 to 11680. Is it dependent on the fixed frequency divider or the reference frequency? How is that range determined?
The divider in the synthesiser allows the VCO to run at frequency which is the division ratio times the comparison frequency. The divider range 11520 - 11680 enables the VCO to operate over the required range.
So the programmable divider and VCO need to be rather fast devices, right? Usual TTL/CMOS counters won't suffice if we need the output signal to be eg. 60 MHz or more?
Why don't we just use the stable reference input frequency directly instead of doing all that for the pll since at the end vco f is same as the reference frequency
Yes, one can wonder why a loop is used to replicate the input frequency. There are, however, a number of ways it can be used. It can create a steady output from a pulsed input. It can be used to detect FM because the VCO voltage is the detected output. It can also be used to create a frequency synthesizer by introducing a divider or mixer into the loop. th-cam.com/video/5K7Pvc5fxZI/w-d-xo.html I hope this helps.
why do we need to lock refclk to VCO output? why can't we just use a VCO directly as a frequency synthesizer and control the output frequency by varying the voltage?
The whole idea of the digital PLL synthesizer is that locking it to a crystal oscillator gives it the high frequency stability of the crystal oscillator. If you just use a voltage controlled oscillator on its own, then it would drift everywhere because there would be nothing to detect and correct any drift in frequency.
hi sometimes we have a rf signal that it's not repeatitive sampling this signals requires a very high samle rate analog to digital converters how can we downconvert this not repeatitive signals and use low sample rate analog to digital converters ? is there anyway?
It is intended to explain how the synthesizers using them work. If you want a video about PLLs, head over to see this video: th-cam.com/video/A9qt0JYdvFU/w-d-xo.html
These videos are reigniting my love for engineering.
That is really great - that is what I am aiming to do. I’m glad you found the video useful.
The very BEST video I've seen so far on how a PLL might work to increase clock frequencies (e.g. inside a FPGA). It isn't bogged down with implementation details, just the top-level concepts. This makes a lot more sense now. You take an input clock frequency (F) and the output frequence will be (F/M)*N, where M and N are integers.
I am really glad you liked the video. I know from my own experience like to start with a top level explanation and then dive down when I understand the basic concepts. Thanks.
Wow amazing. I just needed to learn how PLL works for work but I don't want to spend days learning about the nitty gritty about it. This is the perfect video. Easy to understand and short. Thank you.
I’m really pleased you found the video useful. Thanks for your comment.
In my 14 years experience this concept is little bit confusing to understand but this video makes me understand without any confusion.
That's really great. I'm glad you found the video useful.
thank you, just subbed. it makes 100% sense
my teacher told us to self study that 1 week before exams.
Glad the video helped.
best description of pll
Thank you so much for your comment. Really glad the the video was useful.
Beautifully described thank you.
Thank you for your comment. Glad we were able to help.
Awesome video!
Thanks for your comment. Really glad you found it useful.
Great Explanation!! Keep it up👍
Thanks for your comment. I really appreciate that.
Very concise description, thanks.
Glad it was helpful!
Excellent explanation, yet almost all the information from engineers are basic blocks and superficial reference to the complicated mathematics of the programing of the PLL chip. I have some PLL chips, I need to learn to access and get to run, there isn't any application note for them. Well, the data sheets have basic information for qualified and experienced engineers in the field. But some elaborate examples from talented tutors to newbies, hobbyists, nonexperts would be a hit. Something like setting the chip to default, load with parameters and save a frequency and most important how to extend and expand from this outset. Bringing a PLL chip like the SN761672 or TSA5511 or any other and showing things on the oscilloscope along with frequency counter and a receiver etc.
I confess that I always found the data sheets were a bit lacking. They were of the ilk of "the magic happens here" and no real explanations of how to design with them.
under competition stress they release the part accompanied with mass commercials than support. I guess giant customers get hotline and support once they experience problems.
The best video Now concept clear . Thank you
So glad the video was useful for you. I really appreciate your comment. Thank you.
Amazing explanation sir 💜
Glad you found it useful.
This was great, thank you so much :D
Glad you found the video useful.
Bring us sone numerically controlled oscilator, please.
The digital dividers used between the Vic and phase detector are normally controlled digitally and this means that the frequency of the synthesizer can be programmed by a processor or other digital control.
@@ElectronicsNotes I've been looking at FPGAs, and I see there are templates ("IP") for making PLL circuits in them. I'm now wondering how they make the loop filter, since it's effectively all logic gates. Do they get to skip that part?
I guess the VCO has to be numerically controlled too, not a VCO - presumably just a programmable counter / divider.
@@TooSlowTube I confess that I have never designed a synthesizer using an FPGA. My experience has been designing them using more traditional techniques. Interesting project, though. I would suggest a chat with an RF digital designer who has experience with synthesisers. May be the digital elements are covered both e FPGA and the remainder by analogue circuits.
Could you please explain the ending where the divider range is said to vary from 11520 to 11680. Is it dependent on the fixed frequency divider or the reference frequency? How is that range determined?
The divider in the synthesiser allows the VCO to run at frequency which is the division ratio times the comparison frequency. The divider range 11520 - 11680 enables the VCO to operate over the required range.
So the programmable divider and VCO need to be rather fast devices, right? Usual TTL/CMOS counters won't suffice if we need the output signal to be eg. 60 MHz or more?
Yes, they need to be fast enough to take the incoming VCO frequency.
Why don't we just use the stable reference input frequency directly instead of doing all that for the pll since at the end vco f is same as the reference frequency
Yes, one can wonder why a loop is used to replicate the input frequency. There are, however, a number of ways it can be used. It can create a steady output from a pulsed input. It can be used to detect FM because the VCO voltage is the detected output. It can also be used to create a frequency synthesizer by introducing a divider or mixer into the loop. th-cam.com/video/5K7Pvc5fxZI/w-d-xo.html
I hope this helps.
why do we need to lock refclk to VCO output? why can't we just use a VCO directly as a frequency synthesizer and control the output frequency by varying the voltage?
The whole idea of the digital PLL synthesizer is that locking it to a crystal oscillator gives it the high frequency stability of the crystal oscillator. If you just use a voltage controlled oscillator on its own, then it would drift everywhere because there would be nothing to detect and correct any drift in frequency.
@@ElectronicsNotes thank you sir
MY BELLY BUTTON KEEPS DRIFTING OFF FREQUENCY, IS THERE ANY WAY TO PUT A PLL CIRCUIT IN MY BELLY BUTTON SO IT DOES NOT DRIFT?
I think you need to see your doctor. Belly button drift can be serious. (LoL)
hi sometimes we have a rf signal that it's not repeatitive sampling this signals requires a very high samle rate analog to digital converters how can we downconvert this not repeatitive signals and use low sample rate analog to digital converters ? is there anyway?
Yes, that approach would certainly be possible.
This doesn´t explain anithing on how PLL works
It is intended to explain how the synthesizers using them work. If you want a video about PLLs, head over to see this video: th-cam.com/video/A9qt0JYdvFU/w-d-xo.html