I think that there might be an error in the state machine in the setcion SEND_ADDR6,at the last case SEND_RW. The if statement verify is the counter has reached 2169 ,but I believe that it should be 2168. Taking that in account, all other ifs after this one should be decreased by one. Could you verify this to see if I'm right or not? Also, thanks for this wonderful presentation. I am trying to wrapmy head round all the I2C with FPGA and it'S really difficult.Your video helps alot!
Hi. Thanks for your comments on the video. I am happy to share what I know to help others. I looked into what you said about 2169, and if it should be 2168. I see what you are talking about, and to be honest, it has been too long for me to remember why I put 2169, if it is indeed meant to be 2168 with each one after being decremented by 1. Have you tried it with 2168 and decrementing the following ones? What I know is that the circuit works as is. If there is an error by 1, then it doesn't affect the output. But, if it should be 2168, then I apologize for the mistake, and I appreciate you pointing it out. Have a good one.
@@dajoma36 I agree with you that the difference of one should not make a difference sincethere is no delay accumulation caused by this. I am working through your code in the next days and I suspect that it won't make any difference. Thanks for the fast reply!
Hy...I really like this project and is very usefull for who wants to use the sensor from the board...but I have a question: can you explain how to replace the dumpfile and dumpvars with other file or code?...I have need to simulate and see all the signals in verilog...thank you very much in advance🙏
Hi. Thanks for the comment. The dumpfile and dumpvars are necessary for using Icarus Verilog. If you are using Vivado to simulate, then you can remove the entire initial block with dumpfile and dumpvars. The dumpfile name can be anything you want. As for dumpvars, if you put (0, name_TB), the 0 allows you to access all signals from the test bench down the hierarchy within GTKWave. Hope this answers your question. I recommend checking out the documentation for Icarus Verilog which explains about dumpfile and dumpvars. The docs can be found here: steveicarus.github.io/iverilog/
Hello there actually while I was doing the code for the same but in vhdl,hence I found that the at the beginning it was showing 1 and then it again shows 0 celcius on board while it simulates properly.
So, what I think you are saying is, you wrote this project in VHDL, and it isn't working properly? Sorry, I don't work with VHDL. It works with Verilog. Switch to Verilog?
Hi..Thanks for this video.How can I interface External Temperature sensor to fpga board.I want to read the data from temperature sensor in sdk and write it to pl so that I can do some other operations with this data.
This is not a question with an easy answer. You need to analyze the sensor you want to work with. What sensor do you want to interface with? What communication protocol does it use? UART, SPI, I2C? The data sheet for the sensor will need to be studied to gathered the information needed to develop a circuit to communicate with it. As far as what you want to do with the data, I don't know about sdk and pl. You should be able to interface with the sensor through the FPGA PMOD (GPIO) ports. Hope this helps.
Do you mean that you have just the adt7420 chip? Or do you mean the PMOD with the adt7420? Or do you have an adt7420 on some circuit board from a sensor kit?
@@bogdan13b8 I have not tried this project using the PMOD, but the PMOD is exactly the same set up, so I don't see why it wouldn't work. Give it a try, and please let me know if it does work or not. Again, I think it really should work.
Very well explained, thanks!
I think that there might be an error in the state machine in the setcion SEND_ADDR6,at the last case SEND_RW. The if statement verify is the counter has reached 2169 ,but I believe that it should be 2168. Taking that in account, all other ifs after this one should be decreased by one. Could you verify this to see if I'm right or not? Also, thanks for this wonderful presentation. I am trying to wrapmy head round all the I2C with FPGA and it'S really difficult.Your video helps alot!
Hi. Thanks for your comments on the video. I am happy to share what I know to help others. I looked into what you said about 2169, and if it should be 2168. I see what you are talking about, and to be honest, it has been too long for me to remember why I put 2169, if it is indeed meant to be 2168 with each one after being decremented by 1. Have you tried it with 2168 and decrementing the following ones? What I know is that the circuit works as is. If there is an error by 1, then it doesn't affect the output. But, if it should be 2168, then I apologize for the mistake, and I appreciate you pointing it out. Have a good one.
@@dajoma36 I agree with you that the difference of one should not make a difference sincethere is no delay accumulation caused by this. I am working through your code in the next days and I suspect that it won't make any difference. Thanks for the fast reply!
Hy...I really like this project and is very usefull for who wants to use the sensor from the board...but I have a question: can you explain how to replace the dumpfile and dumpvars with other file or code?...I have need to simulate and see all the signals in verilog...thank you very much in advance🙏
Hi. Thanks for the comment. The dumpfile and dumpvars are necessary for using Icarus Verilog. If you are using Vivado to simulate, then you can remove the entire initial block with dumpfile and dumpvars. The dumpfile name can be anything you want. As for dumpvars, if you put (0, name_TB), the 0 allows you to access all signals from the test bench down the hierarchy within GTKWave. Hope this answers your question. I recommend checking out the documentation for Icarus Verilog which explains about dumpfile and dumpvars. The docs can be found here: steveicarus.github.io/iverilog/
@@dajoma36 thank you...I'll try these 😊
Can I do it with uart protocol? If yes how?
No. The temp sensor is designed to communicate using I2C.
hello, i used your code but when i press the reset button on fpga, it sets all the bits "1" and never changes
Sorry about that. I did mention in the video that the reset does not work properly. The reset logic is incorrect and needs to be revised.
Hello there actually while I was doing the code for the same but in vhdl,hence I found that the at the beginning it was showing 1 and then it again shows 0 celcius on board while it simulates properly.
So, what I think you are saying is, you wrote this project in VHDL, and it isn't working properly? Sorry, I don't work with VHDL. It works with Verilog. Switch to Verilog?
Ok thanks
Hi..Thanks for this video.How can I interface External Temperature sensor to fpga board.I want to read the data from temperature sensor in sdk and write it to pl so that I can do some other operations with this data.
This is not a question with an easy answer. You need to analyze the sensor you want to work with. What sensor do you want to interface with? What communication protocol does it use? UART, SPI, I2C? The data sheet for the sensor will need to be studied to gathered the information needed to develop a circuit to communicate with it. As far as what you want to do with the data, I don't know about sdk and pl. You should be able to interface with the sensor through the FPGA PMOD (GPIO) ports. Hope this helps.
very nice
Hi, I tried converting your code to vhdl from verilog but it is not working now. Can you please help?
I don't do VHDL, what's the point? Verilog is much simpler.
TRY CHAT GPT
Hi, I implemented this in VHDL. Dont listen to OP if you wanna do vhdl, then do vhdl. Personally i find it easy to understand
Your code is not working for zync 7000 zedboard fpga
That is interesting since the Zync 7000 has the same logic fabric as the Artix-7, plus the processor portion.
It doesn't justify whether it will work
can you please upload uart tx rx verilog code ?
I haven't done any UART yet, but when I do, as always, I will upload the code.
Can you upload block design?
You can obtain a block diagram by synthesizing the Verilog and XDC files.
@@dajoma36 thank you 🤗
does this code works with an external adt7420 ?
Do you mean that you have just the adt7420 chip? Or do you mean the PMOD with the adt7420? Or do you have an adt7420 on some circuit board from a sensor kit?
@@dajoma36 i have a pmod TMP2 with adt7420 and i want to connect it to the fpga to read the data from it
@@bogdan13b8 I have not tried this project using the PMOD, but the PMOD is exactly the same set up, so I don't see why it wouldn't work. Give it a try, and please let me know if it does work or not. Again, I think it really should work.
@@dajoma36 it doesn't work, i set the TMP_SDA and TMP_SCL pins to the PMOD HEADER JA, but it does nothing, it shows only zeros
@@bogdan13b8 Sorry that it doesn't work. By all logical accounts it really should work. Maybe there is something else wrong?