Performance Measurement in Xilinx SDK
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- เผยแพร่เมื่อ 13 ก.ย. 2024
- #PerformanceMeasurement #XilinxSDK #ExecutionProfiling #HardwareSoftwarePerformanceComparison
In this video we findout how execution time can be found using the global clock of Zynq SoC. We compare the performance of software-based and hardware-based implementation of the image filtering.
Final source code can be found here
github.com/vip...
Finally, I found what I really wanted to do.
I request you to do more videos on custom IP. Thank you for your great video.
Me too
Hello bro
I do have one doubt, I felt you are the right person to ask.
I want to declare a variable of length 96 bit in HLS. In the HLS guide, it is mentioned to add "ap_cint.h" header and the syntax is uint96 (variable name). Even after including the header, it's showing me 'uint96' could not be resolved. Is there any other way to do this ??
Try int96 instead of uint96
Bro, how performance measurement can be made in vivado HLX?
Similar way. You start the timer before calling the driver api of your hardware. Read the timer once hardware finishes execution (that you can do either using interrupt or by reading some status register). Then find the performance using the same equation. The clock frequency used in this case will be same (irrespective of ur axi clock) since u r using the timer in PS. If you use axi timer in PL to measure the time, should use the axi clock frequency to find the delay
@@TheVipinkmenon ok thank you bro
Hello, I don't have a zynq board but I have vivado toolchain and Xilinx sdk, without having a board is it still possible to validate and analyze the performance of my c code in terms of code size, latency, throughput ?.
Nope. You can't do any software profiling without hardware. Hardware profiling can be done through simulation. Best option will be to buy Zybo board, which is much cheaper.
@@TheVipinkmenon Thank you, Vipin. It has been told me to do without actually having a board. I have developed an algorithm in C and also in VHDL. Using a test bench I can show that my algorithm written in VHDL is working as expected and also I can see post-synthesis reports without actually having zynq SoC. So my question is there any way to show that my C code is working as expected on PS of zynq and also I wanted to ask you that is it possible to create custom IP and accessing that IP from SDK again without having zynq SoC
No. There is no way to test your C code with out actual hardware since Xilinx tools they do not provide a complete simulation model for the processor. They are only providing a bus functional model or verification IP (VIP) in recent Vivado versions. I exactly don't know what is the difficulty for Xilinx in supporting simulation of PS part with a provided elf file. They support assigning an elf file in Vivado but it can not be used for simulation. Instead VIP is used for modelling the processor part, which has all the GP, HP and ACP ports but cannot directly run the elf file. Instead you will have to use predefined APIs available for VIP from the testbench to model your actual software.
@@TheVipinkmenon Yes I agree with you. Thanks a lot for the detailed description.