Verilog For loop : can we synthesis it ? Day 20

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[@radheshyamsharma8994]

Try this to use synthesizable code for loop using always block
integer i;
always @(*) begin
for(i=0 ; i

[@Narayan_BITSPilani]

module top_module(
input [99:0] in,
output [99:0] out
);
genvar i;
generate
for(i = 0; i

[@electro.feedback]

hello sir , Could you please share if the ngspice and xschem with magic are actually used in the insdustries ?

[@Chintu-cx4ir]

Hello sir, Where can I get the PPt you shown in the video containing the daily quiz problem??
I will be great help if you share that too

[@BSrihari-y8p]

Sir can please u explain physical design related subjects.

[@Ozeee22]

Sir I'm not getting to join button in my mobile to join as a member in this channel.

[@venkatasaiharikrishnamaddi]

module tb;
reg a,b;
initial
begin
$monitor("time: %0d, a = %0d b=%0d",$time, a, b);
a = 0;
b = 0;
#10 a = 1;
#10 b = 1;
#5 a

[@whyRD]

A and b will be assigned to 0 in 25 unit seconds

[@venkatasaiharikrishnamaddi]

@@whyRD Not really, A is assigned with 0 at 25 time units and B is assigned with 0 at 35 time units.
I am not getting the reason

[@tamimshikto1710]

sir kindly help me by suggesting an open source full free dft tool, i need to use this in my upcoming thesis related activities🥲

[@whyRD]

According to me you can use any open source tool to simulate dft like ngspice, develop layout for them … they are nothing special then a simple circuit right ? Again i have very limited knowledge about dft

[@tamimshikto1710]

@@whyRDThanks a lot for your kind response! Love from Bangladesh

[@pranayanpratimchandra4575]

@whyRD .. Sir I have sent a request in LinkedIn to connect with you so I can share some doubt over there and can have a proper discussion.

[@whyRD]

Oky sure let me check