Application of Verilog Generate Block | Lets Learn Verilog with real-time Practice with Me | Day 22

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[@abuhuzaifa8764]

Thanks brother...It is very helpful for us...

[@ivogaycaramuti1243]

very very usefull this video. i found it amazing

[@mr_introvert2713]

i am follwing your vedios its excellent understading teching thankyou sir

[@PilatesinSacramento]

Thank you for another great video!

[@Narayan_BITSPilani]

Initially i was not getting correct output for below self written code
module FA(
input a1, b1, cin1,
output cout1, sum1 );

assign sum1 = a1 ^ b1 ^ cin1;
assign cout1 = (a1&b1 | cin1 & (a1^b1));
endmodule
module top_module(
input [99:0] a, b,
input cin,
output reg [99:0] cout,
output reg [99:0] sum );
FA f1 (a[0], b[0], cin, sum[0], cout[0]);
genvar i;
generate
for(i=1;i

[@athiramrs5644]

thanks bhaiya noone goes into the intricate details like you do
i hope your channel grows further more succesfully

[@whyRD]

Thanks lot for this feedback, its means a lot

[@user-yp6gk2js5p]

Thank you Raj, I think you have a mistake in the 4th second, if en=1 it means that a=clk, but you wrote that a=1 while it should be 0 like the clk.

[@nimmanashashankkrishna6114]

exactly same doubt

[@manasmahato3834]

I guess that it is ok a will not change in the 4th sec because in the 4th sec the enable did not change from 1 to 0 or anything it still 1 so a will keep its previous value. it will change in the 8th sec when enable changes from 1 to 0
always@(en) doesn't mean that when en =1 things will execute It means that when en changes the things will get executed
This is according to my thought..

[@nissanbiswas8432]

Thanks sir for your great videos.

[@selfdevelopentchannel6828]

Isn't carry of a full adder of 1 bit? Why is the cout of 100 bits? Could anyone please explain?

[@S_R911]

thanks brother

[@gateaspirant9418]

❤😊