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Thanks, getting to the limit of what is possible with the current layout! I think it was that in Win 3.1 real mode (16 bit 8088/8086) was no longer supported. It needed protected mode (286) or enhanced mode (386), and it was released 6 years after the 386 and 10 years after the 286 were released! Windows 95 only works with 386 or higher. Windows 3.1 was a big improvement on 3.0 (probably should have been 4.0 if Win 95 hadn't started to use that version No.) and the Win32 API support allowed some level of 32 bit code as well. Dave

Thanks, just the Mouse to go then I think I will have a go at re-building with the faster 80C88 and get rid of DMA and the power strip bus connections (these cause most of the reliability issues). Going to play with a few other Windows 1.0 Apps but hope the hard drive doesn't get corrupted. Seems to be intermittent problem where the directory entries and FAT gets corrupted :-( Dave

Thanks, though there are some bits I would do differently next time around. Leave out DMA and more data bus buffering! Thinking about doing a version 2 which SHOULD be a lot quicker! Dave

Thanks, I record the videos partly to remind myself what I did (and for anyone daft enough to try what I am doing). Not always for audience retention/entertainment - sorry. Next project will try to make the videos a bit easier going! Dave

You and me both! Video controllers are by far the most complex part of PCs (old and new). Timings down to 10ns matter even at VGA resolution and despite the best of plans, a certain amount of trial and error. I partly use the videos to remind myself of what I have done (like the Nanocomp snow ones), so not always going to be short and snappy! I think I have reached the limit of Breadboard based PC compatible video controllers. VGA has about 300 registers and dedicated VLSI chips for handling the video logic! (EGA is not much better). I thought MCGA may be an option but Windows driver was 286 only and still in black and white just 640x400 rows, not 640x200! Let me know what you would be interested for the next series? Dave

@@breadboardinglabs I am glad to took my comment in the spirit it was meant! Its a great achievement to get Windows running on a breadboard computer, so hearty congratulations. As for the future, how about returning to the Motorola family with 68008 or full 68000? And if you have had your fill of vintage video controllers, maybe take the easy way out with a Pi Pico or ESP32 VGA solution?

Thanks! If I wasn't so stubborn I would have given up with CGA. I do have a 68008 somewhere, but I also have a new 80C88 which can run at 8Mhz and also a 386DX 33MHz (will need some form of PCB adaptor). May do a BBPC version 2 with 80C88 which should be much easer (and quicker) if I leave out DMA etc. The big issue with any video solution even, with Pico or ESP32 is the register compatibility with VGA and the complexity of 300 registers and associated logic (CGA was simple in comparison). I have been thinking about using a PI Zero and an ISA 5V to 3.3V interface then run some doctored DOSBox or similar virtualization to map the IO registers and RAM via ISA bus to the PI and connect via HDMI. Writing a register compatible VGA or SuperVGA emulator would be a huge amount of work, but mapping IO ports and video RAM on breadboard to GPIO and mangling DOSBOX video code to take inputs from GPIO would be more manageable. Either that or just build Sergey's Trident 9000 VGA card using surface mount chips on a PCB with a ISA to breadboard connector (feels like cheating!). Plenty to think about! Dave

@@breadboardinglabs Are there merits in trying the 80188 or even the 80186 to reduce the chip count? The RM Nimbus (80186-based) ran Windows, but I don't know if it was a special version.

I was trying to use DIP chips initially rather than needing to buy/make PLCC type adapters. I will have to do this for the 386 I have but there aren't any alternatives. The other option is to use a Raspberry PI running an emulator but that feels like cheating! Dave

I thought that using the 74LS646 Buffer/Latch would have made it easier since it can separate the reading /writing of the video RAM from the CPU reading & writing but the fact that the CPU and Video clocks change phase between each other all the time complicates things. Once I had gone back to the Nanocomp approach it wasn't too bad to fix, just wasted a week on the original track. Still using the Cycle 2 Anti Snow period, just controlled differently. Certainly makes me think that using the VGA Clock 25.175 MHz divided by 3 for system Clock may simplify the next version I am planning using a 80C88A which can do 8MHz. The original XT used 14.317 Mhz which was also used for original CGA so they are based on the same clocks too! Got Windows 1.0 running today! Tried Windows 2.0 but the installer trashed the disk FAT! At least I can re-format to 32MB now I don't need to run PC-DOS 2.11 anymore! Thanks for the feedback. Dave

It may seem a bit over the top the explanation but I find it helps a lot to really understand what is going on (if you can't explain it to others...). Will find out later today if it works! Will hopefully publish an update by end of the weekend. Dave

I have based it on the Original IBM XT schematics with some enhancements from Sergey Kiselev's XT design (referenced in later videos) and simplifications from using static RAM and not DRAM. From Sergey's design two Interrupt controllers and real time clock like PC-AT and PS/2 Keyboard/mouse to allow 'modern' PS/2 keyboards and mice to be used since I don't have old XT keyboard or serial mouse. I cover all the bits from the original XT and any enhancements in later videos. Dave

@breadboardinglabs ok

I did a trial run of Windows 1.0 the other day, it works but would be best without the CGA snow and a mouse first! Dave

Glad you enjoy it! Dave

TH-cam suggested that image after upload. Main thing is the video number for those following the series. Dave

They are down to the very fast static RAM 10-15ns, the write signal is a little early before all the address lines have settled so ends up randomly writing to various addresses. Have delayed write by 1/2 CPU clock cycle 115ns and seems to have fixed it. Will publish early next week. Dave

Yes, well just about fixed it all now. Best to do in steps, when I have tried to do everything in one go it results in a big mess! Did a test install of Windows 1.0 today so hopefully will post that next week. Dave

You'd be surprised how useful it is with age appropriate software (with DOS apps being the equivalent of a stone axe and fire I'm sure survival would be possible in the stone age!) . I bet it cold boots to a text editor faster than you can in Windows 11 (recent Windows versions only cold boot on restart, shutdown just does hibernate!). It is a little sluggish, but with DOS software its works pretty well. Just the copying and pasting between applications and multiple apps running which is the big gap (but sidekick TSR etc can handle this too!). What it highlights to me is how bloated most modern software is when workable solutions exist inside and few 10Ks at most 512K if without a pretty GUI. Dave

Well the original CGA card had MC6845 CRTC, Character ROM, 8 RAM + 59 TTL logic chips - 69 Chips in Total. Excluding the RAM, CRTC and ROM the 59 TTL chips have reduced to 22, though 24 if you count the current source and 25Mhz oscillator as chips! My design doesn't do the composite video but does work with VGA display equipment. Dave

Thanks for the feedback. Dave

Yes it really was ahead of its time given the cross platform VM side. Dave

I cover this I think at this point in the video with the extra U90 gate on the DMA Chip Select th-cam.com/video/u8bVg4f31Co/w-d-xo.html In the end I got everything to work without DMA. I may come back to it some time but the Floppy disk is about the only thing using DMA on original PC. Dave

@@breadboardinglabs Apologies. While searching your videos to find some specific information, I stumbled across the part where you describe the bug fixed by U90. It has been a few weeks since I first watched your video and I had no recollection that you were aware of the U90 fix. I did find the webpage where this is explained in detail and was impressed with yet another deep dive into a very niche area of computing design.

The U90 fix just stops DMA controller getting the bus during DMA chip select by the CPU, but didn't stop the stability issues I had with longer floppy disk accesses for DOS 3+. Dave

I bought a bunch of additional DMA chips off eBay (18 I think, they were in packs of 9 and I bought 2!) but I was wasting too much time with DMA so I got the FDC to work with programmed IO with updates to the BIOS. Just needed to bump the CPU clock upto 16Mhz/5.33Mhz so it could read HD floppy disks at 500Kbps which is twice the rate of SD disks like 360K disks. The link for the book is in the descriptions for #32 vtda.org/books/Electronics/The%20Intel%20Microprocessors%20-%20Eighth%20Edition%20-%202008.pdf DMA is about Chapt 13 page 490 I think. Glad you are finding it interesting. I always wanted to do a deep dive into PCs and REALLY understand them. I find the videos useful for my own reference to remember what exactly I did many months earlier! Dave

As I replied in one of your other posts, I dumped DMA for PIO. To use 1.44MB HD floppies I needed 16Mhz/5.33 MHz clock to be able to keep up reading HD floppies. PC DOS 2.0 is much smaller than later versions so has less time for load process to go wrong. I have more detailed analysis of 2.0 vs 3.30 vs 4.00 but not a priority at the moment as want to get CGA card working to run up Windows 1.0/2.0. Thinking about doing a V2 BBPC with modern 80C88 and chips still available new and run in MIN mode at 24/8Mhz, no DMA and a better bus using stripboard and 0.1" headers. Dave

@@breadboardinglabs Yes I have been following all your videos closely and found the DMA videos of particular interest. I don't think there is anything like them elsewhere on YT. Your videos on DOS 2 and DOS 4 compilation were again ground breaking for YT. There are few channels who go so deep into specific technical details and I am aware just what level of knowledge that this takes. I enjoy your videos for this reason and have learned quite a lot which will be very helpful if I revisit my own 8088 project.

Thanks for the feedback. It has taken quite a while to fully understand the more complex aspects but fortunately I have more time now to spend on this. May do a Version 2 which should be much quicker to do and not quite as detailed for the more casual viewer rather than the dedicated ones such as yourself. Dave

Ah well done with those purchases. I only started my own PC collection with a 486 DX in around 1992 and unfortunately I cleared out all of the old ISA & PCI cards etc more than a decade ago :-(

Agreed, and in fact to get the floppy disk controller working with programmed I/O (not DMA) I had to overclock the 8088 I have from 1983 to 16Mhz for it to be able to keep up with 1.44MB High Density Floppy drive data rate (500Kbps). PC Jr and Tandy 1000 only needed to use programmed I/O for standard density floppy drives so based frequency was OK (250Kbps). Dave

I agree. I use the Busboard Prototype systems (Ben Eaters recommenation) ones which I get from Mouser in batches of 10 or more (£7-8). They are more expensive but I have found them to be reliable. It would be good to have 0.6" wide gaps and tabs at each end to join them. Also bus rails say in 8's without the gaps you get with the power rails. Steer clear of the cheaper boards, they will waste a lot of time. Dave

Your welcome, I'm glad its of interest. I would be doing this anyway for fun out of a personal interest, its just the videoing overhead and editing (and checking subtitles) which is the least fun part! Dave

Thanks, will have to try Tetris on the 8088 Breadboard PC after the 6809. Dave

Well the electronics experts say you can't build anything reliable on Breadboards so I'm here to prove them wrong! Dave

The prep is a bit of a drag but worth it in the long run in my experience. Thanks for the feedback. Dave

I can't claim these being my idea. Grant Searle did a load which I reference in this video on the chip label topic th-cam.com/video/oadHWpas3p0/w-d-xo.html His labels are at searle.x10host.com/labels/ChipLabels.pdf Hope this helps. Dave

Its a bit of a pain the first time you use a symbol but moving components around in a diagram to get the best layout is much easier than physical re-wiring. Dave

@@breadboardinglabs I agree, I've been doing the same and it does make if MUCH easier indeed

Not got into FPGAs yet, I would be interested in the CGA design. No chance of making a VGA compatible controller with DIP chips but with an FPGA it should be possible. The videos take less time now I have got used to the process. Normally takes about 3 hrs after recording content including a number of reviews, thumbnails and chapter timing. Reviewing and correcting the subtitles is the most time consuming part even with DaVinci Resolve generating them in a few minutes. The TH-cam default autogenerated subtitles aren't very accurate for technical content like my videos. My experience with DOS booting was similar, read the first sector OK but after that the flaky DMA stopped the rest loading. PC DOS 2.2 did work some of the time because it was so much smaller than DOS 3.30+ (though the floppy disk format was odd - 1.44MB formatted in PC DOS 2.2 as 360K format!). PIO Mode FDC worked pretty well once I boosted the clock to 16MHz so it was fast enough to keep up with 1.44MB FDC (Tandy 1000 and PC Jr did not have to deal with data from High Density disks at 500KHz, only worked at 250KHz). I think in next generation design with 80C88 able to do 8MHz+ just need to switch to Turbo mode for FDC access in the BIOS. Dave

The only problem with the DIP FDC is that it doesn't output the disk change signal. I will have to kludge something with a PLD to do this. At the moment the BIOS is hacked to no disk change which is fine for booting but not for swapping disks about! DMA was a massive waste of time. Once clock speeds got to 8-10Mhz the CPU could process data faster than the archaic DMA controller used in the PC (better ones were available at the time but cost drove the use of the 8237). Mine worked some of the time but after swapping out 4 of the chips I gave up and switched to Programmed IO. Will remove DMA from future iterations and switch the Min mode too I think. Dave

"Although I have looked over the IBM PC schematics quite closely, I never noticed that a wait state was added for IO read and write. After some searching I found this possibly incorrect statement in StackExchange "OTTOMH The original 8088 4.77MHz IBM PC had 4 wait states for I/O and 2 wait states for memory". I am keen to understand this, so will have to dig deeper. From your explanation, a single wait state for I/O accesses seems correct. Perhaps I will have to get my scope out? Timings for IOR and IOW for maximum mode from the 8288 might have different timings as compared to minimum mode. This is something I can scope out on my 8088 PC motherboard." The default 8088 timing is 2 clock cycles (T3 & T4 periods) for memory and IO read/write which is about 400ns (419ns with 4.77MHz). The XI 8088 design has a flip-flop U30A & U24 which takes XIOR and XIOW and adds 1 clock cycle by providing -RDY/WAIT to 8284 clock. This changes the IOR and IOW to 600ns. An increase in 200ns. I know this because that's what I measure in logic analyzer. When I unplug -RDY/WAIT the IOR and IOW time goes back to 400ns. The XT schematics system sheet 2 has U70 and U88 which also has inputs from XIOR and XIOW and outputs to -RDY/WAIT and looks like it should add 200ns too but can't verify as I don't have an original XT but schematic looks the same as XI 8088. I think the StackExchange reference is not correct (or confusing wait states for clock cycles for memory). The default read/write for IO and Memory is 2 clock cycles (minus about 60-75ns according to 8088 datasheet). The gates identified above I think add 1 more clock cycle for IO, to make 3 clocks (600ns) or 1 wait state TW between T3 and T4. Third party memory expansion boards using slower DRAM could have used the READY bus signal to add more wait states to off board memory from what I understand. On board RAM was 200ns access time so didn't need wait states. "In my own 8088 design, I decided to use "minimum" mode, to avoid the need for the expensive bus controller (8288). So I was just checking the datasheet for the width of IOR and IOW which come from the CPU. By chance I have used the faster "-5" ICs in a number of places, so that probably helps them meet the IOR/IOW width timings. I used an 8253-5, even though I have a 8254 in my "Intel box", which seemed to be an older device from 1980. Still you have given me "food for thought". TBH I didn't analyse the timings in any way when I designed my minimal 8088 system, which is a little embarrassing :-( ." I am thinking of getting a modern CMOS 80C88 and trying to re-build in min mode and see if I can avoid needing any of the 8284 and 8288 chips but maintain PC compatibility. Will still need legacy timers like 8253/8254 and PIC etc. But will use programmed IO instead of DMA which just needs faster clock than 4.77MHz which modern chips support. Perhaps my search skills are poor, but I'm not finding any YT videos or web pages which show the ISA timings in detail on a scope or logic analyser. Some stuff here on timing regarding CGA from martypc.blogspot.com/2023/05/exploring-cga-wait-states.html?m=1 They also did work on other timing like DMA etc. Hope this helps. Dave

I checked the datasheets and logic analyzer output again. 8253 is min 400ns read & write time. With default 4.77 MHz clocks with no wait states the PC is about 419ns so it SHOULD be OK without wait states. Since I have changed the main clock frequency to 16 MHz and dropped the IO wait states for getting floppy disk programmed IO working, the timer still seems to be OK even though this may only be 375ns read/write now. Issues may have been caused by data bus needing another buffer in parallel which I added. Sometimes it is not always clear what fixes things. Can't always do changes one at a time! Dave

Hopefully this will be easier/quicker than MDA video controller but experience shows it probably wont!

I'll remember to release future videos around the same time then!

Ah not thought of that! I never really got into DEBUG but I can see with the assembler/disassembler you could pretty much do most things with it (as long as in 1 64K segment). Other than what was in the MS-DOS reference for DEBUG there was no real other source of good info for this sort of thing at the time. I think I got a Compuserve account in the early 90's but nothing like what can be found on the Web. Dave

@@breadboardinglabs With debug we can create executable com files with a size limit of 64 kb, but the code can order more free memory from DOS to load more code and data into the memory. We start with DS=CS=SS and all free memory, but we don’t know wich memory location is free to use or reserved for driver and DOS. So we have to calculate how many bytes our executable need at minimum to give all other memory back to DOS before we can order free memory(4kb at minimum) from DOS.

Thanks for the clarifications around BASIC versions. I agree with your 3.3 assessment, no help, very few switches on commands. MS-DOS 5.0 was way more complete with help and /? on most/all commands. I may upgrade to 5.0 for future videos. Dave

Not sure the ch340 drivers would works with Motorola 6809? Needed something simple so PS/2. Also for Breadboard 8088 PC needed something which the XI 8088 BIOS knows about. There are SOME USB DOS drivers knocking about but nothing I have seen suitable for BIOS. Thanks for your thoughts. Dave

Thanks, the CGA should be OK. I suspect getting the memory Map right for MCGA high res 640x480 2 colour and 320x200 256 colour will be tricky with a 6845 CRTC. In the 6809 version I didn't have to worry about PC compatibility so used 8 row address lines to get the 480 horizontal lines. MCGA used contiguous addresses for the pixels due to use of dedicated LSI chips. Still thinking about that one but will probably use a EEPROM to do the CPU memory map decoding. Dave

Thanks for the feedback. I would have to admit that so far I have not done anything to promote the channel. Its more of a video diary of how I build the project, which I have used on several occasions when I have forgotten what I did previously! I even impressed myself on one occasion! I will perhaps look to re-build the breadboard PC when I get Windows 1/2/3 running. I'll then perhaps put more effort into promotion! Feel free to mention on Hacker news or similar 😉 Thx Dave

My observation is that with every increase in complexity, fewer people watch the videos. I think that's a shame too...

I'll do a TH-cam short on it for all those with short attention spans!

Well I change the chip layouts to the physical layout so that the schematic layout matches the breadboard layout (approximately!). Avoids having to worry about PCB side in KiCad. Drawing the wires in KiCad is easier to do and change than on the breadboard. Helps to identify bottlenecks and where things get too busy. I find the schematics used for PCBs with just the labels on the pins difficult to follow. Dave

Yes they are well built machines, almost a work of art if you like this sort of stuff! Mine was from a former colleague who was going to chuck it out! Is a Pentium III as well so not quite the 386 but still a useful machine with floppy disk and IDE drive useful for testing old components! I noticed the picture still has some grubby marks around the button even after giving the outside a good clean! Dave

The E signal uses the same logic as used by the IBM PC, it just uses and PLD rule E = (!IOR # !IOW) (The IOW and IOR are active low). So E is low unless a read or write is in progress. I suspect the Motorola style chips only need the E signals when being read or written too, so as you say no direct relation with the PC clock (other than via IOR and IOW). Dave

I am not really sure! I FDISKed and formatted the drive again and it works as C:\. It could be related to the BIOS Parameter block info which goes in the OS Boot sector (not the MBR) but that is just a guess! The code in DOS which deals with floppy disks and hard disks seems to have lots of kludges in it to work around various hardware issues (and number requested by IBM from DOS 4.0 source). Main thing is it works! I will be digging into MBR/Partition table and OS boot sector in subsequent videos. Dave

Glad you liked it!

Thanks, still a little way to go, CGA Video and Windows 1,2 & 3 to try yet! Dave

All I remember when I did this was that getting rid of GPT was tricky and fdisk/mbr using Win 95 boot disk didn't do it. CLEAN ALL seemed to do it faster than DBAN. Not sure I can be bothered to re-install Windows on a disk just to try it out again! Dave

Fortunately our cat is more interested in laps and sleeping by my feet. No bench invasion so far in the last 2 years! There is the occasional need to go around the multiway Dupont to reseat them but surprisingly reliable for a spaghetti PC! Dave

Wow, that's some feat to watch all of them! The Github stuff needs an update and be aware that the DMA stuff doesn't work reliably. I will be updating the schematics over the next few weeks now that the worst of the KiCad 8 bugs seem to have been fixed in 8.04 (was crashing for me after every other bus line update). If you are looking to build PCBs you could try using Sergey Kiselev's XI 8088 which I have borrowed quite a bit from (and the BIOS). github.com/skiselev/xi_8088. Feel free to use what you want otherwise. Thanks for the feedback. Dave