วีดีโอ

Was there any reason why you preferred the RISCV32i chip over an x86 chip in QEMU? I appreciate the lesson in cross compiling too, but was curious why. Thanks for making these. 10/10

I like your teaching method 🫡

1. General Purpose Registers: Temporary storage for data and addresses during processing. Used for arithmetic, logic, and data transfer operations. 2. Stack Pointer Register: Points to the top of the stack in memory. Manages function calls, local variables, and return addresses. 3. Program Counter (PC): Holds the address of the next instruction to execute. Ensures sequential or branched program flow. 4. Arithmetic Logic Unit (ALU): Performs arithmetic (add, subtract) and logic (AND, OR) operations. Core component for data processing. 5. Central Processing Unit (CPU): Executes instructions from programs. Comprises ALU, registers, and control unit for processing tasks. 6. Control Unit (CU): Directs operations of the CPU. Fetches, decodes, and executes instructions, coordinating other components.

Enjoyed the session a lot sir! GDB Dashboard is truly amazing! 🔥

Just what I was looking for ! I'm sure that this series is going to be a blast ! Please don't stop the series in the middle and thanks a lot !

What is the software name you are typing ?

This is what I actually needed in life today.. thanks a tons..

Great content!!

Hallo from Germany. Great tutorial. how does the print get to execute if std.io.h only includes the header files? isn't the linker has to link the cop file?

Anyone here learning cpp😅

In embedded systems, **I/O memory** refers to the memory-mapped I/O (MMIO) regions that are used to communicate with hardware peripherals. Unlike general-purpose memory, which stores data and instructions for the CPU, I/O memory is dedicated to interfacing with hardware devices such as GPIOs, UARTs, timers, ADCs, and other peripherals. ### Key Concepts of I/O Memory in Embedded Systems: 1. **Memory-Mapped I/O (MMIO):** - In MMIO, hardware peripherals are mapped to specific memory addresses in the system's address space. - The CPU interacts with these peripherals by reading from or writing to these memory addresses, just as it would with regular RAM. - For example, writing to a specific address might configure a GPIO pin, while reading from another address might retrieve the status of a UART. 2. **I/O Registers:** - Hardware peripherals typically have a set of registers that control their behavior. These registers are mapped to specific memory addresses. - Examples of registers include: - **Control Registers**: Configure the operation of the peripheral (e.g., enable/disable, set modes). - **Status Registers**: Provide information about the current state of the peripheral (e.g., data ready, error flags). - **Data Registers**: Hold data being transferred to or from the peripheral (e.g., UART transmit/receive buffers). 3. **Volatile Keyword:** - In C/C++, I/O memory is often declared as `volatile` to prevent the compiler from optimizing away accesses to these memory locations. - This is necessary because the value of I/O memory can change at any time due to external hardware events, and the compiler should not assume it can cache or optimize these accesses. Example: ```c volatile uint32_t* const UART_STATUS_REG = (uint32_t*)0x4000C000; volatile uint32_t* const UART_DATA_REG = (uint32_t*)0x4000C004; ``` 4. **Accessing I/O Memory:** - To interact with a peripheral, you read from or write to its mapped memory addresses. - Example: Reading a status register and writing to a data register: ```c // Wait until UART is ready to transmit while (*UART_STATUS_REG & UART_TX_READY) { // Polling } // Send a byte of data *UART_DATA_REG = 'A'; ``` 5. **Memory Protection and Privilege Levels:** - In some systems, access to I/O memory may be restricted based on privilege levels (e.g., user vs. kernel mode). - Embedded operating systems or bare-metal firmware must ensure proper access to I/O memory to avoid unauthorized or unintended modifications. 6. **Peripheral-Specific Addressing:** - Each peripheral has its own set of registers and memory addresses, which are defined in the hardware datasheet or reference manual. - Developers must carefully follow the documentation to correctly configure and use the peripherals. ### Example: GPIO Control Suppose a GPIO peripheral is mapped to memory addresses starting at `0x40020000`. The control register for GPIO pin 5 might be at `0x40020014`. To set pin 5 as an output and drive it high: ```c #define GPIO_BASE_ADDR 0x40020000 #define GPIO_CR_OFFSET 0x14 #define GPIO_ODR_OFFSET 0x18 volatile uint32_t* const GPIO_CR = (uint32_t*)(GPIO_BASE_ADDR + GPIO_CR_OFFSET); volatile uint32_t* const GPIO_ODR = (uint32_t*)(GPIO_BASE_ADDR + GPIO_ODR_OFFSET); // Set pin 5 as output *GPIO_CR |= (1 << 5); // Drive pin 5 high *GPIO_ODR |= (1 << 5); ``` ### Challenges in I/O Memory Management: - **Address Alignment**: Some peripherals require aligned access (e.g., 32-bit writes to 32-bit aligned addresses). - **Concurrency**: In multi-threaded or interrupt-driven systems, race conditions can occur if multiple tasks access the same I/O memory. - **Endianness**: The byte order of data in I/O memory must match the hardware's expectations. ### Summary: I/O memory in embedded systems is a critical concept for interacting with hardware peripherals. It involves memory-mapped registers that control and communicate with devices. Properly managing I/O memory requires understanding the hardware's memory map, using `volatile` to prevent compiler optimizations, and following the peripheral's documentation for correct usage.

AMAZING VIDEOS

Awesome as all the videos 👍👍🔥

Awesome content 👍👍 Keep up!

Super amazing stuff 2.0❤‍🔥❤‍🔥

💘💝💖💗💓💞💕💟❣💔❤‍🔥💌

Waiting for c runtime

Hello bro just saw the this video and I cant wait to start the course, the roadmap is unconventional which is why I think its the most awesome one, please dont stop uploading such great content ❤❤❤

can you provide the link here for the repo

The power of c made you blush in the end :P

Great video bro

Keep going sir!

It's very helpful for understanding big picture of systems, iam waiting for next cpu mental model

I know nothing about programming and taking a C++ course, does everything you say in this video basically mean the same thing for C++

Please keep uploading

Ohhh.. looking forward for those lectures ....Subscribed

Great also make more videos on Linux device drivers ❤

looks promising .. saved the playlist .. and subscribed 😃

Very helpful !!

The GitHub Repository is available here: github.com/pyjamabrah/c-language

Real good video, keep it up. Probably compile them all into a one shot course after you finish. With multiple examples of sys calls, networking and low level controls included.

waiting for the next one, nice thumbnail. Hoping the new approach works

I learnt embedded from you, liked it so much that I connected with you on LinkedIn. I know C but I'm still gonna put my friends on to this. Big ups!

i was exactly looking to relearn the c language from the fundamentals .this is the need of the hr for me .hope this course gets a lot of engagement and wont stop in mid .intro looks promising

This is a hidden gem for all C lovers!

eagerly waiting for the course

Bruh I like this gonna follow it

Hello sir, curious to know which device you use to teach our write on the screen

Good to C you back in action !!!

I'm a student who fascinated about embedded systems and I found this as gem. Thanks for this video