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Hi!👋

What lies? BOTH single steps - that’s the whole point :)

Thank you ☺️

What, i2c?

@@AndersNielsenAA No. I²C on on a huge 6502 system.

I think you’ll find a billion devices disagree :)

No. The 65C02 simply doesn’t mind stopping the clock completely - so you can essentially just use a (debounced) button instead of the input clock. Edit: It can still use the circuit though

5550? :D

@@AndersNielsenAAlol!

Indeed, and there are no CMOS 6507s out there - that’s still “pretty fast” though, so I guess the myth started because it’s not immediately obvious to everyone that means you can halt it indefinitely and move it forward with a push of a button. And it’s also in all the manuals :)

Thank you :)

Sure! Just emulate RISCV in 6502 and emulate x86 in RISCV.. kinda slow tho

Sure! Just emulate RISCV in 6502 and emulate x86 in RISCV.. kinda slow tho

Absolutely maybe!

I think it’s more about the fact that you don’t really need it to pause as you can just latch whatever the 6502 wants to offload to a register pretty easily on the ~W signal if you want to inspect what’s coming out. But that’s basically what you said :)

And somehow people still forgot - it’s also in the original MOS HW Manual :)

@@AndersNielsenAA my first computer was a Kim-1. I had to make my own power supply. My second computer was Apple II serial number 000745. I was 15 years old and I worked at The Byte Shop in Englewood Colorado. 8-)

@@andrewowens5653 Sounds like some great memories

I think the Z80 doesn’t mind being clocked at 1Hz but I haven’t dug into it. And I think you’re right it doesn’t have a sync pin 📍

@@AndersNielsenAA It does have an equivalent to SYNC: M1 together with MREQ indicates an opcode fetch cycle. There seems to be no minimum clock frequency. From the manual: "When the clock input to the Z80 CPU is stopped at either a High or Low level, the Z80 CPU stops its operation and maintains all registers and control signals." So it looks like you can single-cycle a Z80 by either method -- stop the clock, or use WAIT.

Well neither of those actually apply. On the Asian markets it’s super easy to get both - but the CMOS versions are a bit more expensive. Much more if going for a new one. Interfacing should be the same except the 90s versions run faster. Then there’s also the whole CMOS software incompatibility thing between manufacturers.. and HW incompatibility for the WDC version too

You are very close :)

So, like the Altair 680?

The issue is that the registers need a clock to keep refreshing their state. The way you would typically stop a CPU and make it single step would be to stop the clock signal. This is how it was handled later when it was a static register. The board here doesn't stop the clock signal, it instead latches the signals which allow the CPU to fetch instructions. It's still getting clocked and still refreshing the register states, but it is waiting for the bus to be free to read, hence a single step.

That’s incorrect. All the 6502’s put the data bus into high Z half the cycle - the 6502 and 6510 are the same in that regard. And this actually does let us halt after each CPU cycle.

@@AndersNielsenAA the 6502 has no tri-state capability. this is proved by the fact that C64 engineer employed a 6510 cpu which is a 6502 with integrated bus tristate capability (AEC signal) plus one memory mapped hw port

@@gasparinizuzzurro6306 The 6502 databus tristates. The address bus does not. I take advantage of that on my ABN6502 SBC.

@@AndersNielsenAA so not a full tristate functionality. it always require a custom electronic around it.

@@gasparinizuzzurro6306 Plenty of tristating to single cycle and feed it instructions. You don’t need to tristate the address bus for that. The 6502 won’t do anything at all without support circuitry. It’s a CPU. Anything except the most basic address decoding requires more circuitry. Doing the same thing on a 65c02 would also require a minimum of an IC to stop the clock in the right state - so you might as well use the same circuit and leave the clock running. And the 6510 is NMOS just like the 6502 so it needs a running clock too.

Thank you and thank you for the insight! The way the circuit is setup relies heavily on the button’s DPDT nature and makes it harder to control digitally - or just with SPST buttons. A few more logic ICs like you did would certainly make it more versatile and robust. The 6502s can differ quite a bit when it comes to the reset - I’ve heard some of the NMOS ones can overheat if held in reset for too long so a short reset pulse is very important too. Luckily I’ve never experienced that with a 6507. I appreciate having access to your Perseus schematics very much so I can sanity check a few things while moving forward, thank you 🙏 :)

@@AndersNielsenAA Thank you very much. To explain my case in detail, when I powered on the CPU board with the RDY signal at a “L” level and in a stop state, CPU reset, and then proceeded with the step operation, it occurred with a certain probability that the execution address progress was not correct. In this case, I believe that the start vector setting within the CPU is not correct. So, I think this kind of problem does not occur in the case of a configuration where the first state is always RUN state by power-on reset. I had to solve this problem with my PERSEUS-7, because it is assumed that it is often operated in step operation only, not in RUN state at all from power-on. I have made four PERSEUS-7 units and verified the operation with multiple CPUs as well, and confirmed that it is not a defect in only one unit by chance. defect occurred on a Rockwell NMOS R6502A and not on a CMOS R65C02. The R65C02 has a different number of clocks before the first instruction execution and I believe has an improved reset sequence. The additional circuit that solved the defect is R54 in PERSEUS-7 and R4 in PERSEUS-8.

@@mitsuruyamadaThank you for the details. Since Sync stays low during reset, I wonder if it would be sufficient to ensure “single instruction mode” during reset. I guess that would do the same as keeping it in run state - but of course that means you can’t read the reset vector the CPU reads either way.

​@@AndersNielsenAA Thank you very much. You are right. According to the datasheet, it is sufficient to maintain “single instruction mode” even during RESET. This phenomenon and the countermeasure is based on my personal experiment. I have not been able to reproduce the defect within the conditions and number of times I have re-tested now. Since this circuit allows the same number of dummy steps until the first program instruction for the R6502A and the R65C02, I am going to continue evaluation with this circuit. Thank you again.

If you were banned from Lemon64 it wasn't because you were just trying to debunk myths. As long as you showed evidence and stayed civil then you wouldn't have been banned.

​@@AureliusR I can give you a copy of no less than 500 posts Groepaz left there that were directed at me that were all personal attacks including questioning my mental health. Everyone has their limits. What you say is patently false. He was an acquaintance of TNT and that is the only reason it ended the way it did. In any case it resulted in me selling more than 200k$ worth of merchandise that according to him should not have worked and caused damage to C64. All false. Added edit : The document titled 'The C64 PLA Dissected' by Thomas 'Skoe' Giesel proved everything I said was true and all the disparage from Groepaz was lies.

It requires quite a bit more effort than most believe - and a lot of love for the subject and patience with externalities :) Constructive dialogue is great - if people aren’t nice it’s easy to disregard :)

@@AndersNielsenAA Groepaz became very offensive with me around 2008 when I indicated ST's M27C512-90B6 PROM chip (only 1$ US at Mouser back then) had a low slew rate on output and therefore did not generate the glitches other 27(C)512 would cause when used as a PLA replacement for the C64. He was involved with Individual Computers' SuperPLA V3 which sold for about 30 Euros so this would have been a significant loss of market. I had proof from logic analyzers from the university where I was studying but couldn't take the results out. Eventually the genuine Super Zaxxon cartridge became the litmus test. The ST chips were discontinued in 2011 and would have saved huge sums to C64 users. See video from MindFlareRetro : #10 'The PLAin Truth About the Commodore 64 PLA' at World of Commodore 2017

@@AndersNielsenAA Groepaz became very offensive with me around 2008 when I indicated ST's M27C512-90B6 PROM chip (only 1$ US at Mouser back then) had a low slew rate on output and therefore did not generate the glitches other 27(C)512 would cause when used as a PLA replacement for the C64. He was involved with Individual Computers' SuperPLA V3 which sold for about 30 Euros so this would have been a significant loss of market. I had proof from logic analyzers from the university where I was studying but couldn't take the results out. Eventually the genuine Super Zaxxon cartridge became the litmus test. The ST chips were discontinued in 2011 and would have saved huge sums to C64 users. See video from MindFlareRetro : #10 'The PLAin Truth About the Commodore 64 PLA' at World of Commodore 2017

Well - both, hence the instruction/cycle switch :) But I know what you mean - titles are hard..

@@AndersNielsenAA yes there are two hard problems in computer science, cache invalidation, naming, and off-by-one errors.

@@jxtq27 Not the 0th time I’ve heard that one ;-)

Gotta admit - at that point my hands would be tingling to grab the modern 16bit logic analyzer :) …but no break points though

I'm sure there's better options, but I'd be itching to see how much can be done without specialized tools. ("We did it with the wrong tools, as a joke")

I did mention it in the video - if the clock gets below about 10 kHz the registers start getting corrupted :)

@AndersNielsenAA Sorry didn't notice that.

@@MCPicoli np :) I still don’t have a complete picture of how exactly the registers lose their contents on a silicon level - but I plan to find out :)

@@AndersNielsenAA The register state is held in capacitors, like a dynamic RAM. The charge leaks away and has to be refreshed periodically.

Section 1.4.2.3 of the MCS6500 Hardware Programming Manual shows it was absolutely an intentional feature - and where Woz got it from :)

It doesn't - but you don't need it to single cycle. It works fine with just the RDY pin :)

Absolutely - they used the RDY pin to slow down execution just like the description in the 6500 datasheets. My point here is the 65C02 is often credited as the only chip you can use on a breadboard and step one instruction forward at a time - but actually the NMOS 6502 has the RDY pin for exactly that purpose and has no limits as to how long you can pause between instructions if you keep the clock running. ...and then I show how to do it :)

Why bother driving a classic car when newer ones exist?

Fancy 16 bit registers and everything. No no, I like the budget friendly 6502 ;-)

You could argue that working with any 1970's CPU is just wasting your time, as is whining on videos about them.

@@bryede I think he’s joking 🙃

That's the trick here, that the clock never stops.

Absolutely! It's been a few years since I wrote that and I wouldn't make the blunder today - but I can't believe I didn't catch it myself while making the video XD

james sharman spotted!

@@skmgeek Shh, nobody would ever guess I watch retro electronics videos.

Lol

I’m not completely sure and you may be right I stretched the comparison between DRAM and SRAM over to registers a bit too far. Woz actually ran into the issue with the Apple II - he thought he could keep the clock high while refreshing RAM because it was faster than the spec for a cycle - but he missed that keeping the clock high for a whole cycle at 10kHz is essentially 5kHz.. and he started losing registers. He kept swapping to new 6502s because brand new ICs have greater register capacitance than slightly used ones - it worked for a little while.. I bet he was real happy to switch to CMOS :)

@@AndersNielsenAA so we really talk about the non-temporary registers? So even for NOP the 6502 goes through A X Y SP on instruction load and refreshes a capacitor? I don’t see the metal lines for this. Intel had a register file and a refresh counter just below. And for each cycle (or instruction) this counter would advance. Ah, so on clock low registers live forever? To check if real registers are lost we need to keep the clock high for long and sta something with an addressing mode with z or t or SP . Then record the address bus. Then execution the same instruction, but with short high. If Y survived, we now record the correct address . This tests AH and AL . Or is it some trick with the instruction pointer? Or ALU input: LDA, CMP, PHA . Slow and fast . Test TAX … In a way 6502 is dynamic: it uses a line of inverters to delay the clock to create 4 phases. The clock edge needs to be sharp, not jitter. I don’t think that there is a Schmidt Trigger . I know that Intel and others need two clock pins with non-overlapping phases. I feel like this is mandatory for static operation. So 65C02 has two clock pins? In the end CMOS is mostly great for battery life because at that feature size leakage was zero and energy consumption also while holding a phase. I would like to see a joule thief where the 65c02 uses solar power and reduces it clock at dawn until it stops. Just wanted to add: static CMOS must not have an overlap where PNP and NPN both conduct. I guess that 1.1 V core voltage 5 GHz CPUs don’t really care that much. I also wonder how old discrete CMOS avoided this at 12 V max on the rails. Scrap that slow clock. Even a CMOS circuit on solar power needs a clean step clock edge and enough energy in an accompanying capacitor to run a full physical cycle ( but not a whole instruction).

@@ArneChristianRosenfeldt Neither - in those 1/10.000ths of a second you need to pass both phases. I’ve seen NOP running continuously slower than 10kHz without the program counter losing count - but something is out of spec for sure. Not completely sure what’s going on at the silicon level - would love a detailed description - but I am guessing it is in some way caps leaking.

@@AndersNielsenAA I found that in the NES: The sprite memory in the PPU is DRAM, but its refresh is the same as evaluation. Nintendo is explicit about it as Intel. Weird that MOS is not. I should check visual 6502 if the bits use 6 transistors or 1. DRAM needs sense amps and an SRAM buffer. AH AL only serve as buffers. I read that the MOS designers were speed freaks who wanted to squeeze the most MHz out of their ancient fab / large feature size for yield. So with 8 transistors an SRAM bit could be put to the middle between low and high (turn off power) then connect to the bus (phase change), and then power up feedback (delayed phase ). I babbled on in my last comment.

@@ArneChristianRosenfeldt You’re certainly digging into a deep subject I’ve only scratched the surface of - I guess I should go deep with Visual 6502 some time :) I appreciate the thoughts, thanks! 😊

Thanks - I think the Z80 has static registers and doesn't mind stopping the clock. I guess technically you could use this circuit just for debouncing and hook it up to the clock - but less would do :)

@@AndersNielsenAA Thanks for that. I'd be looking to use this for stepping through old Z80 and 6502 arcade PCBs to see what makes them tick. Before the likes of custom chips were a thing.

@@phils_arcade In that case you would probably need a bit more work for the Z80 in circuit since you would have to manually do all the steps. But maybe you get some inspiration on how to make that happen on a breadboard from this :)

Z80 has an M1 pin that signals when the CPU is fetching an instruction so plenty of designs are around that single step it.

The E&L MT-80Z "The Fox" trainer has a single-step setup built in. Which works just fine.

Thank you! :)

Thank you. Yes, it's not a very durable design. Same for most other larger keys - they really should've put a metal bracket to hold them but I guess it's another cost cutting measure.

​@@AndersNielsenAA they sold it for a really outrageous price.

Good question. It has very distinct spring mechanism providing the switching.. but on the other hand it’s still a membrane keyboard. Both and neither I guess.

@@AndersNielsenAA Model Ms used a membrane too and folks would usually consider that mechanical (due to the buckling spring). I'd consider it mechanical.

@@colinstu Usually the distinction is made between individual switches vs a membrane but it doesn’t really make much sense as a measure of “quality”. You can find plenty of horrible mechanical switches and some great rubber dome keyboards too - I can’t handle 20 minutes of typing on a C64 keyboard no matter how “mechanical” it is ⌨️ 😆

I love mechanical keyboards and I'm a big fan of the old Model M. I was surprised to find out they had membranes under the buckling springs. I feel like a Coca-Cola fanatic who finds out they've been drinking Pepsi all this time without realising. All I can say is they _feel_ mechanical. I guess that's the main thing, right?

And it even has software now :)

@@AndersNielsenAA Cool 👍🏿

I like that perspective :)

@@AndersNielsenAA well how else should it be describe? The only way to make it more in line with it is to include basic with a keyboard

There’s a link to it on my GitHub in the description :)

@@AndersNielsenAA I see the github just kinda overwhelmed but it. I think I need to use a arduino and then just build some stuff together. But not sure where to start I was given a 5150 project and while it works it needs a keyboard 😀

Yes, of course. The demo you see here erases the ROM, burns a new one, and reads it back for comparison - you can skip the first two parts ;-)

Thanks for your support! :)

Not the easiest to port to as it doesn’t have 5V tolerant IO - wouldn’t be too hard to make a RPDuino with level shifting tho :)