Hi I'm still learning to use cadence I have an issue with simulation I'm using salama otra model to design rc sinusoidal oscillator and I'm using 180nm technology and passive components of values R1= 10k , R2= 1k, C1&C2=100p & 1n F and for the biasing current I'm using idc component of value 80uA. I'm using vdc instance for supply voltages VDD and VSS .I'm using 1.8v for my supply voltages and I'm using same instance for my gate baising voltage and I'm using +0.5v for my nmos gate biasing and - 0.5v for my pmos gate biasing After doing the transient analysis I'm getting a ramp signal instead of sinusoidal signal. Even though i tried every way still facing the same problem. I hope u see this comment.🙂
Sir I am working on CMOS double tail comparator. Through this way can I find out input and output noise for the entire comparator design?
hello, how choose the value of dc source from gates? (1.8V , 0.8V , 0.4V)
Hi
I'm still learning to use cadence
I have an issue with simulation
I'm using salama otra model to design rc sinusoidal oscillator and I'm using 180nm technology and passive components of values R1= 10k , R2= 1k, C1&C2=100p & 1n F and for the biasing current I'm using idc component of value 80uA.
I'm using vdc instance for supply voltages VDD and VSS .I'm using 1.8v for my supply voltages and I'm using same instance for my gate baising voltage and I'm using +0.5v for my nmos gate biasing and - 0.5v for my pmos gate biasing
After doing the transient analysis I'm getting a ramp signal instead of sinusoidal signal.
Even though i tried every way still facing the same problem.
I hope u see this comment.🙂
reachout via mail with schematics pic and this comment
@@MudasirMir7 I've send you mail.