You're a life saver My professor doesn't know how to explain this very well Don't get me wrong, he knows his stuff But he just isn't good at teaching Thanks to you i actually got an A on the test
I've searched everywhere for better explanations on this subject, and I am so incredibly glad that I stumbled upon your videos. They are fantastic and I sincerely thank you for creating and sharing these!
Thank you thank you thank you, that was so simple and informing and you did a wonderful and great job demonstration l. PLEASE continue making these videos.
I really liked the first two videos, but this one is very confusing. One thing I don't understand is why this circuit is called a latch when it does not latch actually. The difference in its behavior is clear when compared to the previous video (#2). This circuit does not work with pulses (see 2:28). It requires that the D input is already latched/sustained in order to operate like the latch it is supposed to replace (gated SR latch). The output Q is latched only as long as the Set button (D input) is sustained. Up to this point, Q acts as a buffer for D without any latching properties. It doesn't only fix a problem of gated SR latch, it also changes its operation. Another problem I see in this explanation is the behavior of the E input which is a little bit different here. In the previous video, the role of the E input was only to enable or disable the functionality of the set and reset buttons/signal. In this circuit the E input has also another function. It can affect/change the output (see 4:19 , 5:58 and 6:13). Anyone care to clear up my confusion?
@@ComputerScienceLessons it's a shame i wasn't able to find a JK flip-flop video on your channel. Don't get why is supposed to be acting as a toggle at 1 1. The funny thing is that my teacher wasn't able to explain it to me :D
@ComputerScienceLessons tried IT not worked with stability Used all push down resistors except the data that was directly yo VCC with a pullup Made a latch with trqnsistors
I don't understand why when we have D=0 and En=0 we continue getting Q=0 . If I am correct , after the 1st upper NAND we get 1 and after the first down NAND we get 1 . How can we determine then that Q=0 ??? It isn't obvious from the logic diagram of NAND...Anyone help please ??
Hi David. If you watch my playlist on DRAM, you will see that decoders and multiplexers are covered to some extent in parts 3 and 4. :)KD th-cam.com/video/I-9XWtdW_Co/w-d-xo.html
Quite literally the best resource on the internet. No unnecessary information, straight to the point, simply done, and animated. THANK YOU for this
You're a life saver
My professor doesn't know how to explain this very well
Don't get me wrong, he knows his stuff
But he just isn't good at teaching
Thanks to you i actually got an A on the test
I've searched everywhere for better explanations on this subject, and I am so incredibly glad that I stumbled upon your videos. They are fantastic and I sincerely thank you for creating and sharing these!
These videos made my Digital Electronics class so much easier to follow. Thank you.
You are welcome KD:)
These are high quality videos, thanks for the clear explanation.
I got fed up by cringy Indian tutorial videos..finally found these videos your a real life saver
I haven't understood a word out of those Indians. This man is a life savior.
yeah those indiggas are annoying...
One of the best composed lessions I've seen
Thank you so much! Finally understand timing diagrams because of this video
Thank you, The video was very patient and concise in explaining the concepts and was very useful
You are most welcome. Glad to help :)KD
You are actually a hero, thanks so much
Bless you, sir, you are my hero.
Thank you. Glad to help :)KD
You saved my life.
Thank you thank you thank you, that was so simple and informing and you did a wonderful and great job demonstration l. PLEASE continue making these videos.
You are most welcome - and thank you :)KD
I LOVE YOU! ♥♥♥
You are so good at teaching this! I LOVE YOU! ♥♥♥
💖 :)KD
The best channel ♥♥♥ thank you doctor ♥
Thx a bunch siri genuinely appreciate your work
You are most welcome :)KD
best video to explain D latch
Amazing explanation, simple words, nice animation, and informative video. Many thanks.
Beautiful honestly
You're very kind. Thanks :)KD
I finally understand gated d latches. Thank you!
I really liked the first two videos, but this one is very confusing. One thing I don't understand is why this circuit is called a latch when it does not latch actually. The difference in its behavior is clear when compared to the previous video (#2). This circuit does not work with pulses (see 2:28). It requires that the D input is already latched/sustained in order to operate like the latch it is supposed to replace (gated SR latch). The output Q is latched only as long as the Set button (D input) is sustained. Up to this point, Q acts as a buffer for D without any latching properties. It doesn't only fix a problem of gated SR latch, it also changes its operation. Another problem I see in this explanation is the behavior of the E input which is a little bit different here. In the previous video, the role of the E input was only to enable or disable the functionality of the set and reset buttons/signal. In this circuit the E input has also another function. It can affect/change the output (see 4:19 , 5:58 and 6:13).
Anyone care to clear up my confusion?
cramming before my dig logic final tmr thank you
You are welcome. The best of luck to you :)KD
Great information! Than you for all the help!
great explanation man. thanks a lot
You're very welcome :)KD
thanks for sharing with us
you are such a nice teacher ،
You're welcome. Naughty students might disagree with you. :)KD
These are excellent videos thank you very much
Terrific. Really terrific.
Thank you. :) KD
This is beautiful
2:29 Hey, shouldn't this only be an and gate, not a nand gate please? For the inputs, not the SR latch part
This is awesome
Thank you :)KD
@@ComputerScienceLessons it's a shame i wasn't able to find a JK flip-flop video on your channel. Don't get why is supposed to be acting as a toggle at 1 1. The funny thing is that my teacher wasn't able to explain it to me :D
Have you written any books on the subjects? Computers?
Remarkable!
i have subscribed you with 2 accounts. Thank you sir
You're welcome. You're welcome :)KD
Looks like the lines between the NAND gates should be red at t=91s. Am I wrong?
nice video thanks
Bravo!
Thank you :)KD
thank you so much dude
You're welcome :)KD
thank you so much for your effort
That unpredictability could be useful in ways can it? That has the potential to be an A randomizer of sorts.
can d latch only be with nand gates?
Can you show the Boolean expressions and talk a little bit about them
I'll take a look at it :)KD
Sir, I love you.
Love you too. :)KD
you are amazing
Thank you :)KD
the enable can be used witha push button to alternate tue outs between 0-1 like a switch?
indeed
@ComputerScienceLessons tried IT not worked with stability
Used all push down resistors except the data that was directly yo VCC with a pullup
Made a latch with trqnsistors
thank you
You are welcome :)
what.. before you said the nand gated SR latch is active low.. because both S & R are always high..
Excellent
Thanks for the videos :)
You're welcome :)
very informative,thank you.
Thank you for the feedback. :)
excellent thank you!
I don't understand why when we have D=0 and En=0 we continue getting Q=0 . If I am correct , after the 1st upper NAND we get 1 and after the first down NAND we get 1 . How can we determine then that Q=0 ??? It isn't obvious from the logic diagram of NAND...Anyone help please ??
extremely useful,tks
U R Welcome
If you were my teacher I would have the best grades I've ever had
You flatter me. Thank you :)KD
thanks alot!!!!
I have to log in to say thank you.
You are very welcome. Your comment is greatly appreciated.
What about the jk flip flop
Should have a video on this in a couple of weeks - I hope. Rather busy with the day job at the moment I'm afraid :)KD
@@ComputerScienceLessons were can i learn for Multiplexer and decoders
Hi David. If you watch my playlist on DRAM, you will see that decoders and multiplexers are covered to some extent in parts 3 and 4. :)KD
th-cam.com/video/I-9XWtdW_Co/w-d-xo.html
It's good
best ever!!
I will buy you a dinner for saving my life.
If we ever meet, mine's a cheeseburger :)KD
Molto interessante, ma le tecnologie in inglese non è facile capirle
Mi dispiace ma il mio italiano non è buono. Forse puoi tradurre le didascalie.