FFT based Frequency Detector using an FPGA -Intel Quartus (IT WORKS!!)

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ความคิดเห็น • 12

  • @guywaldron580
    @guywaldron580 3 ปีที่แล้ว

    Would the ADC board used in your project be suitable to collect low powered RF transmissions (if it was connected to a suitable antenna) or would the signal have to be amplified first? Also, could you provide a link to the Learning Central site as I haven't been able to find it.

  • @aussieknowhow
    @aussieknowhow 3 ปีที่แล้ว

    Thanks for a very informative video, it helped a lot of things click for me. A couple of questions if you don't mind? What is the clock frequency (40.96MHz) actually related to, is it the frequency the FFT module is running at, I'm sturggling to visualise how the FFT creates its range of frequencies from that. Also, where in your process does the windowing occur and how is it set. In the explanation it looks like one sample goes into the FFT module and one sample comes out. How/where is the FFT run over a windowed amount of samples? Sorry if I'm misunderstanding something.

    • @VisualElectric_
      @VisualElectric_  3 ปีที่แล้ว +2

      The clock is chosen so the FFT bins are centred at frequencies with rounded numbers. If the clock is 40.96 MHz and you have an FFT size of 4096, the bins will be at 10,000 Hz intervals, e.g. DC, 10,000, 20,000...etc. Since the FFT is a power of 2, you sometimes end up with a weird clock frequency to give you these rounded bin centres.
      With the Intel FFT Megafunction, you have to load in samples 1 at a time. Once all samples are loaded in, there is a short latency period and your FFT results start to come out 1 at a time. The start of packet and end of packet flags determine the window of the FFT, so you set SOP on the 1st sample and EOP on the last. In this example, I have a streaming FFT so the next window starts straight away and it continuously processes window after window. There's a nice timing diagram on the intel FFT Megacore user manual.

    • @aussieknowhow
      @aussieknowhow 3 ปีที่แล้ว

      @@VisualElectric_ Aewsome, thanks for that.

  • @RITESHKUMAR-sk7tp
    @RITESHKUMAR-sk7tp 2 ปีที่แล้ว

    Hey, can you tell me how to implement the I/FFT circuit in SPICE? I am trying to make a image reconstruction circuit.

  • @ramchanderbhaskara301
    @ramchanderbhaskara301 4 ปีที่แล้ว +1

    Hi! Great content. Can you provide the source files, please? I am working on to build a similar setup on a Xilinx platform. Help!

  • @TymexComputing
    @TymexComputing 11 หลายเดือนก่อน

    The F-ForFast FT is always DFT - no need to ambiguate :)

  • @SatishKumar-yn8tr
    @SatishKumar-yn8tr 3 ปีที่แล้ว

    Can u send any link where steps to use fft inbuilt block I mean IP core in quartus. Please help if u know. I want to learn this.

  • @pradeepreddy4842
    @pradeepreddy4842 3 ปีที่แล้ว +1

    Can you share the code?? Actually I have to develop the similar project.. Could you help me

  • @wui9869
    @wui9869 ปีที่แล้ว +1

    hey,could you please share your code project ?thanks a lot

  • @crazyengineer52
    @crazyengineer52 3 ปีที่แล้ว

    Wooooow amazing work , Am really impressed,, million of thanks Sir, But could you please share me your files code and tell me which Quartus version are you using ?!, Is it Lite or Standard ,,, Please I need your help