LARGEST Digital Filter on an FPGA - design, build and test of an FIR filter. How big can we go?

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  • เผยแพร่เมื่อ 29 ต.ค. 2024

ความคิดเห็น • 7

  • @Magnom365
    @Magnom365 3 ปีที่แล้ว +1

    Also you’ve got a very soothing voice. Reminds me of Matthew Walker!

  • @jimbobsbin
    @jimbobsbin 6 หลายเดือนก่อน

    Nice one my dude, found this very helpful

  • @breedj1
    @breedj1 3 ปีที่แล้ว

    Excellent video

  • @jordd6206
    @jordd6206 2 ปีที่แล้ว

    Great vid

  • @Magnom365
    @Magnom365 3 ปีที่แล้ว

    Awesome content! Subbed!

  • @AkbarRajaei
    @AkbarRajaei 2 ปีที่แล้ว

    good job

  • @hightlightlol2106
    @hightlightlol2106 2 ปีที่แล้ว

    Do you think the response of the filter can be observed by the network analyzer, I know these ADC have different range of Vref but if we calib the nework analyzer to make input and output signal linear (in some bandwidth) we can observe the s21 in a better way. I will try it but Im using the lite edition of the Quatus and Im not sure the FIR IP Catalog can work on lite version
    Btw I have exactly the same hardware as your, the CGX starter board is so convenient that it have USB to UART to controll stuffs inside the FPGA. I just complete my own NCO project and control the freq through the USB-UART port. There still so much things to explore on this board!