Thanks for watching! TSMC CoWoS is the same technology as 2.5D with different name and I already made video for 2.5D. Please check below link and let me know if you still have some questions. 2.5D - th-cam.com/video/EuBRa3NWMPs/w-d-xo.html
No, TMV and InFO are different each other. TMV(Through Mold Via) uses package substrate and makes via through mold. You can find package cross section picture at below link(At page 4 of PDF file). c44f5d406df450f4a66b-1b94a87d576253d9446df0a9ca62e142.ssl.cf2.rackcdn.com/2018/02/PoP_DS586.pdf amkor.com/technology/package-on-package/ InFO(Integrated Fan Out) does not use package substrate and uses RDL(Redistribution Layer) for electrical connection. You can find package cross section picture at below link. 3dfabric.tsmc.com/japanese/dedicatedFoundry/technology/InFO.htm
Hey there. Great video! Do you know what the equivalence of Samsung's FO-WLP method, first introduced with the Exynos 2400, is by TSMC? As far as I understood, InFO is also a Fan Out stretegy, but I'm having a hard time understanding whether the WLP applies to it as well 😅
First of all thanks to share this information and I missed this news. I think TSMC InFO is equivalent to Samsung FO-WLP which was used for Samsung Exynos 2400 and both of them used WLP. But detailed structure and process flow are different each other. Probably Samsung FO-WLP was made by Samsung Foundry. Please check below links from Samsung and you will find Samsung FO-WLP information. semiconductor.samsung.com/processor/mobile-processor/exynos-2400/ # At the middle of page there is "Plays hard. Runs fast. Stays cool." then click "Learn More". You will have new window then go to 2nd page by clicking arrow on the right. You will see the picture of FO-WLP structure. semiconductor.samsung.com/solutions/technology/package/ # Please scroll down to the bottom then you will see the pictures of FOPLP anf FOWLP.
very clear! ipressive how they got rid of the carrier as it was simply replaced by the mold. Question and correct me if I am msitake. In this exaple of process, only one single die is used. In order to make the A10 ship, we will require the positionning of an other die (memory). this second die will be stacked on ton of this package from the side of the "seed layer" and will connect via the IN-FO plating. Did I understood properly?
Memory die is packaged and that package is placed on top of A10 package. So it is PoP, Package (Memory) on Package (A10). For connection between memory package and A10 package, your understanding is correct.
@@semicontalk3223 thank you for specifying that the memory die needs to be packaged as well before placement, otherwise that would be a completely different problem Thank you :)
Thank you for the video! Great as usual! Could you please explain the RDL a little bit more? e.g. Structure, connection with die (in 7th step in this video)? Thank you very much!
RDL stands for redistribution layer and it is Cu layer. Purpose of RDL is to connect die pad and solder ball electrically if solder ball should be located apart from die pad. RDL is made by electroplating process and usually RDL thickness is around 3~10um. RDL is electrically isolated by dielectric material e.g. PI, PBO, BCB and PI (Polyimide) is the most popular material. If there is 1 layer RDL its structure will be dielectric layer at the bottom, RDL in the middle, dielectric layer at the top, total 3 layers.
Excuse me, may I ask that does the process flow in this video belong to the die first process flow in previous video "Fan Out Wafer Level Package"? and the order of the carrier removal step seems different in these two videos, which one is better?
There are 3 major fan out processes, 1. Die first, die up, 2. Die first, die down, 3. Die last. InFO uses 1. Die first, die up and the die first process in "Fan Out Wafer Level Package" uses 2. Die first, die down. It is difficult to say which one is better because each process flow has different advantage and each company uses their process because they have more experience for that process.
Thank you for your very well informative video. But, as far as I know, the case is only for InFO type PoP. I am so much wonder the other type of InFOs, -R and oS and AIP ... . Also, here is quick question, what is the big difference between InFO and CoWoS. Both are implementing in Back-end phase, but the order of deploying the "chip(die)" seems different. Chip(active die) first for InFO and Chip(active die last for CoWoS, I found the information in somewhre of internet. But it is not clear, would you please tell us the big difference, with video if you can please. BTW Thank you again for the video. PS, your pronunciation and accent are not bad at all, never.
Thanks for kind encouragement on my pronunciation. ^-^ Here are differences between InFO and CoWoS. InFO is a fan out package which does not use package substrate but uses RDL instead for electrical interconnection of dies. Typically InFO is for small package. Popular example is application processor of Apple iPhone. CoWoS is a 2.5D package which uses silicon interposer for electrical interconnection of dies. CoWoS also uses package substrate. Typically CoWoS is for large package. Popular example is GPU + HBM of nVIDIA. Please also check below videos for your information. [TSMC InFO] th-cam.com/video/v8obQndavuI/w-d-xo.html [Fan Out Wafer Level Package] th-cam.com/video/R7ssguwtef4/w-d-xo.html [2.5D Package Technology] th-cam.com/video/EuBRa3NWMPs/w-d-xo.html If you have more question please let me know.
@@semicontalk3223 Thank you for your reply, But as I understand, InFO-oS and InFO-L use the package substrate as TSMC share at HC33. Also, all of CoWoS types(R/S/L) use the RDL for electrical interconnection of dies. So I can't find difference in this context at all. If I'm wrong please correct me. I've already watched and reviewed your whole related videos. Thank you for the additional references.
Thanks for explanation. [InFO family] - InFO family is based on fan out technology. 1. InFO : Fan Out package without package substrate, typically for 1 die. 2. InFO-R (Also called as InFO_oS) : R means RDL and oS means on Substrate. InFO is attached on package substrate (InFO_oS), typically for 2 dies or more. 3. InFO-L (Also called as InFO_LSI) : LSI means Local Silicon Interconnect. It has same package structure with InFO-R or InFO_oS except LSI, local silicon interconnect. LSI is a small Si(silicon) bridge like Intel EMIB and it connects between dies and interconnection density of LSI is much higher than RDL, means better performance. LSI is embedded within mold compound of RDL structure. [CoWoS family] - CoWoS family is based on Si(silicon) interposer technology. 1. CoWoS-S (In the past, it was just called as CoWoS because there were no CoWoS-R and CoWoS-L at that time.) : 2.5D package. It uses Si(silicon) interposer and Si interposer is attached on package substrate. 2. CoWoS-R : R means RDL. CoWoS-R has same package structure with CoWoS-S except RDL. It uses RDL instead of Si(silicon) interposer which is lower cost. 3. CoWoS-L : L means LSI, Local Silicon Interconnect. It has same package structure with CoWoS-R except LSI which is a small Si(silicon) bridge like Intel EMIB. LSI is embedded within mold compound of RDL structure. You can find some pictures at below links for better understanding. 3dfabric.tsmc.com/english/dedicatedFoundry/technology/cowos.htm hc33.hotchips.org/assets/program/tutorials/2021%20HotChips%20TSMC%20Packaging%20Technologies%20for%20Chiplets%20and%203D_0819%20publish_public.pdf
@@semicontalk3223 Thank you for kind explanation. Well, I'm not still clear the difference between InFO-X and CoWoS-X. But refer to many referneces, it is better to understand InFO from a fan-in or fan-out point of view, rather thatn comparing it with CoWos from a chiplet point of view. Of course there some variant of this technology like as, InFo-L, InFO-SoIS and InFo-SoW(Tesla Dojo1) which are technologies that is still developing. They make me confused to categorize and discriminate, but I think someday TSMC will organize those various concepts. By the way, some reference tell me that the order of implementing chiplet for advanced packiging is the difference between InFo and CoWoS. In more details, Info process put chip first before the implementing RDL layer and CoWoS put chip last after the implementing RDL. I guess the CoWoS way is better for yield of packaging processing since less process phases. But I'm not sure. Please let me get a very specific question, Q1) Does InFO-R(oS) doesn't use the silicon interposer? I'm pretty sure it has RDL layer according to you gave the hc33 reference p11. But I'm so confused what type of base material(layer) where the RDL layer is implemented. I thoght the InFO-oS(R) also use the Si interposer for the RDL implementing. Doesn't it? Q2) Also, regarding your explanation about CoWoS-S/R, you mentioned that CoWoS-S doesn't use the RDL but only -R use it. However, refer to the Wikichip( en.wikichip.org/wiki/tsmc/cowos ) CoWoS-S also has AI RDL, I don't get an idea of AI but it seems obvious that it is RDL. Rather the difference between CoWoS-S and CoWoS-R is type of interposer, CoWoS-S with Si interposer and CoWoS-R with organic interposer, according to paper from TSMC at ECTC21( ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9501754 ). I'm not an expert that can tell the detailed difference between organic interposer and Si interposer. Thank you vrey much for the discussion anyway.
Let me answer for your questions. A1) You are correct and InFO-R(oS) doesn't use silicon interposer. RDL layer is implemented on mold compound. A2) There is nothing at the Wikichip(en.wikichip.org/wiki/tsmc/cowos). Yes, the difference between CoWoS-S and CoWoS-R is type of interposer, CoWoS-S with Si interposer and CoWoS-R with organic interposer. Would you send the link about Al RDL you are referring to ?
Do you think we can replace the use of interposers with advanced WLP (>500 I/O and small microbumps)? What's the advantage of 2.5D over a fan out WLP design?
Maybe we can use fan out instead of 2.5D for some applications but not all. 2.5D with Si interposer can make less than 1um line and space and has better electrical performance than fan out so it is usually used for high performance applications like networking and data center. But it is more expensive than fan out. Usually, fan out can make line and space down to 2um and used for mobile like application processor and power management. So 2.5D and fan out have different target area and different advantage.
![[Eng Sub] PoP(Package on Package): Qualcomm, Apple, Samsung - MCeP, InFO, iPoP](http://i.ytimg.com/vi/FU62n4S9VEk/mqdefault.jpg)
This is the best video for learning TSMC's Info packaging. Thank you so much! Could you make a video for CoWoS, too?
Thanks for watching! TSMC CoWoS is the same technology as 2.5D with different name and I already made video for 2.5D. Please check below link and let me know if you still have some questions.
2.5D - th-cam.com/video/EuBRa3NWMPs/w-d-xo.html
@@semicontalk3223 Got it. Thank you so much. Sorry I had to ask, but could you make a video about TSMC's SoIC?
I will but I already got some requests so I will make after those.
Thank you very much for the video! it's very clear !!
Thanks for watching!!!
Thanks for the great content. I have a doubt - Is TMV and InFO are same technology?
No, TMV and InFO are different each other.
TMV(Through Mold Via) uses package substrate and makes via through mold. You can find package cross section picture at below link(At page 4 of PDF file).
c44f5d406df450f4a66b-1b94a87d576253d9446df0a9ca62e142.ssl.cf2.rackcdn.com/2018/02/PoP_DS586.pdf
amkor.com/technology/package-on-package/
InFO(Integrated Fan Out) does not use package substrate and uses RDL(Redistribution Layer) for electrical connection.
You can find package cross section picture at below link.
3dfabric.tsmc.com/japanese/dedicatedFoundry/technology/InFO.htm
Hey there. Great video! Do you know what the equivalence of Samsung's FO-WLP method, first introduced with the Exynos 2400, is by TSMC?
As far as I understood, InFO is also a Fan Out stretegy, but I'm having a hard time understanding whether the WLP applies to it as well 😅
First of all thanks to share this information and I missed this news. I think TSMC InFO is equivalent to Samsung FO-WLP which was used for Samsung Exynos 2400 and both of them used WLP. But detailed structure and process flow are different each other. Probably Samsung FO-WLP was made by Samsung Foundry.
Please check below links from Samsung and you will find Samsung FO-WLP information.
semiconductor.samsung.com/processor/mobile-processor/exynos-2400/
# At the middle of page there is "Plays hard. Runs fast. Stays cool." then click "Learn More". You will have new window then go to 2nd page by clicking arrow on the right. You will see the picture of FO-WLP structure.
semiconductor.samsung.com/solutions/technology/package/
# Please scroll down to the bottom then you will see the pictures of FOPLP anf FOWLP.
감사합니다 ~ 많은 도움이 되었습니다
시청해주셔서 감사합니다.
very clear! ipressive how they got rid of the carrier as it was simply replaced by the mold.
Question and correct me if I am msitake.
In this exaple of process, only one single die is used.
In order to make the A10 ship, we will require the positionning of an other die (memory). this second die will be stacked on ton of this package from the side of the "seed layer" and will connect via the IN-FO plating.
Did I understood properly?
Memory die is packaged and that package is placed on top of A10 package. So it is PoP, Package (Memory) on Package (A10). For connection between memory package and A10 package, your understanding is correct.
@@semicontalk3223 thank you for specifying that the memory die needs to be packaged as well before placement, otherwise that would be a completely different problem
Thank you :)
Thank you for the video! Great as usual! Could you please explain the RDL a little bit more? e.g. Structure, connection with die (in 7th step in this video)? Thank you very much!
RDL stands for redistribution layer and it is Cu layer. Purpose of RDL is to connect die pad and solder ball electrically if solder ball should be located apart from die pad. RDL is made by electroplating process and usually RDL thickness is around 3~10um. RDL is electrically isolated by dielectric material e.g. PI, PBO, BCB and PI (Polyimide) is the most popular material. If there is 1 layer RDL its structure will be dielectric layer at the bottom, RDL in the middle, dielectric layer at the top, total 3 layers.
@@semicontalk3223 Thank you very much for your kind explanation. Now I can unterstand the whole process much better.
Excuse me, may I ask that does the process flow in this video belong to the die first process flow in previous video "Fan Out Wafer Level Package"? and the order of the carrier removal step seems different in these two videos, which one is better?
There are 3 major fan out processes, 1. Die first, die up, 2. Die first, die down, 3. Die last. InFO uses 1. Die first, die up and the die first process in "Fan Out Wafer Level Package" uses 2. Die first, die down. It is difficult to say which one is better because each process flow has different advantage and each company uses their process because they have more experience for that process.
Thanks for your kind reply. Does die up or die down mean the direction of die pattern? If pattern face down, doesn't it destroy the pattern?
Yes, it is the direction of die pattern. No, face down does not destroy die pattern.
Thank you very much 🙏
Thank you for your very well informative video. But, as far as I know, the case is only for InFO type PoP. I am so much wonder the other type of InFOs, -R and oS and AIP ... .
Also, here is quick question, what is the big difference between InFO and CoWoS. Both are implementing in Back-end phase, but the order of deploying the "chip(die)" seems different. Chip(active die) first for InFO and Chip(active die last for CoWoS, I found the information in somewhre of internet. But it is not clear, would you please tell us the big difference, with video if you can please.
BTW Thank you again for the video. PS, your pronunciation and accent are not bad at all, never.
Thanks for kind encouragement on my pronunciation. ^-^
Here are differences between InFO and CoWoS.
InFO is a fan out package which does not use package substrate but uses RDL instead for electrical interconnection of dies. Typically InFO is for small package. Popular example is application processor of Apple iPhone.
CoWoS is a 2.5D package which uses silicon interposer for electrical interconnection of dies. CoWoS also uses package substrate. Typically CoWoS is for large package. Popular example is GPU + HBM of nVIDIA.
Please also check below videos for your information.
[TSMC InFO]
th-cam.com/video/v8obQndavuI/w-d-xo.html
[Fan Out Wafer Level Package]
th-cam.com/video/R7ssguwtef4/w-d-xo.html
[2.5D Package Technology]
th-cam.com/video/EuBRa3NWMPs/w-d-xo.html
If you have more question please let me know.
@@semicontalk3223 Thank you for your reply,
But as I understand, InFO-oS and InFO-L use the package substrate as TSMC share at HC33.
Also, all of CoWoS types(R/S/L) use the RDL for electrical interconnection of dies.
So I can't find difference in this context at all.
If I'm wrong please correct me.
I've already watched and reviewed your whole related videos. Thank you for the additional references.
Thanks for explanation.
[InFO family] - InFO family is based on fan out technology.
1. InFO
: Fan Out package without package substrate, typically for 1 die.
2. InFO-R (Also called as InFO_oS)
: R means RDL and oS means on Substrate. InFO is attached on package substrate (InFO_oS), typically for 2 dies or more.
3. InFO-L (Also called as InFO_LSI)
: LSI means Local Silicon Interconnect. It has same package structure with InFO-R or InFO_oS except LSI, local silicon interconnect. LSI is a small Si(silicon) bridge like Intel EMIB and it connects between dies and interconnection density of LSI is much higher than RDL, means better performance. LSI is embedded within mold compound of RDL structure.
[CoWoS family] - CoWoS family is based on Si(silicon) interposer technology.
1. CoWoS-S (In the past, it was just called as CoWoS because there were no CoWoS-R and CoWoS-L at that time.)
: 2.5D package. It uses Si(silicon) interposer and Si interposer is attached on package substrate.
2. CoWoS-R
: R means RDL. CoWoS-R has same package structure with CoWoS-S except RDL. It uses RDL instead of Si(silicon) interposer which is lower cost.
3. CoWoS-L
: L means LSI, Local Silicon Interconnect. It has same package structure with CoWoS-R except LSI which is a small Si(silicon) bridge like Intel EMIB. LSI is embedded within mold compound of RDL structure.
You can find some pictures at below links for better understanding.
3dfabric.tsmc.com/english/dedicatedFoundry/technology/cowos.htm
hc33.hotchips.org/assets/program/tutorials/2021%20HotChips%20TSMC%20Packaging%20Technologies%20for%20Chiplets%20and%203D_0819%20publish_public.pdf
@@semicontalk3223 Thank you for kind explanation.
Well, I'm not still clear the difference between InFO-X and CoWoS-X. But refer to many referneces, it is better to understand InFO from a fan-in or fan-out point of view, rather thatn comparing it with CoWos from a chiplet point of view.
Of course there some variant of this technology like as, InFo-L, InFO-SoIS and InFo-SoW(Tesla Dojo1) which are technologies that is still developing. They make me confused to categorize and discriminate, but I think someday TSMC will organize those various concepts.
By the way, some reference tell me that the order of implementing chiplet for advanced packiging is the difference between InFo and CoWoS. In more details, Info process put chip first before the implementing RDL layer and CoWoS put chip last after the implementing RDL. I guess the CoWoS way is better for yield of packaging processing since less process phases. But I'm not sure.
Please let me get a very specific question,
Q1) Does InFO-R(oS) doesn't use the silicon interposer? I'm pretty sure it has RDL layer according to you gave the hc33 reference p11. But I'm so confused what type of base material(layer) where the RDL layer is implemented. I thoght the InFO-oS(R) also use the Si interposer for the RDL implementing. Doesn't it?
Q2) Also, regarding your explanation about CoWoS-S/R, you mentioned that CoWoS-S doesn't use the RDL but only -R use it. However, refer to the Wikichip( en.wikichip.org/wiki/tsmc/cowos ) CoWoS-S also has AI RDL, I don't get an idea of AI but it seems obvious that it is RDL. Rather the difference between CoWoS-S and CoWoS-R is type of interposer, CoWoS-S with Si interposer and CoWoS-R with organic interposer, according to paper from TSMC at ECTC21( ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9501754 ). I'm not an expert that can tell the detailed difference between organic interposer and Si interposer.
Thank you vrey much for the discussion anyway.
Let me answer for your questions.
A1) You are correct and InFO-R(oS) doesn't use silicon interposer. RDL layer is implemented on mold compound.
A2) There is nothing at the Wikichip(en.wikichip.org/wiki/tsmc/cowos).
Yes, the difference between CoWoS-S and CoWoS-R is type of interposer, CoWoS-S with Si interposer and CoWoS-R with organic interposer.
Would you send the link about Al RDL you are referring to ?
Do you think we can replace the use of interposers with advanced WLP (>500 I/O and small microbumps)? What's the advantage of 2.5D over a fan out WLP design?
Maybe we can use fan out instead of 2.5D for some applications but not all.
2.5D with Si interposer can make less than 1um line and space and has better electrical performance than fan out so it is usually used for high performance applications like networking and data center. But it is more expensive than fan out. Usually, fan out can make line and space down to 2um and used for mobile like application processor and power management. So 2.5D and fan out have different target area and different advantage.
wow info package
I dont understnd his english pronunciation... wht the hell
Thanks for feedback and I will practice more.
I turned on captions at times. Very informative videos. Thanks