W/L of pmos will be 10 as it is 2 or 3 times more than that of nmos W/L since holes mobility is less so in order to provide the same current the total area i.e W/L is increased
Happy diwali sir your lectures concept series is really helpful and valuable to us , upcoming VLSI Engineers ... Respect ur efforts love from Delhi ❤️❤️👍🏼😊
W/L for pmos should be 10 or more than that because mobility of nmos is double the pmos so in order to maintain the same flow of current through both nmos and pmos we always kept the (W/L) p = 2(W/L) n
if W/L of NMOS is 5 the W/L ratio of PMOS is 10. The sizing is done in such manner because the mobility of holes is 2times less than mobilty of electrons. This is done so that the resistance offered to current, by PMOS and NMOS remains the same.
If the (W/L)n= 5 then then the (W/L)p should be multiple of 2 to 3.5 of NMOS this is due to mobility the speed of PMOS is lesser than the NMOS ,to increase the speed and they can match each other we keep the (W/L)p PMOS 2 to 3.5 more of NMOS
We want a mosfet right , so if we have forward biased pnp instead of it , out purpose of having only mosfet will defeat, in logic level it wont work as we wanted to
W/L of pmos will be 10 as it is 2 or 3 times more than that of nmos W/L since holes mobility is less so in order to provide the same current the total area i.e W/L is increased
Happy diwali sir your lectures concept series is really helpful and valuable to us , upcoming VLSI Engineers ... Respect ur efforts love from Delhi ❤️❤️👍🏼😊
W/L for pmos should be 10 or more than that because mobility of nmos is double the pmos so in order to maintain the same flow of current through both nmos and pmos we always kept the (W/L) p = 2(W/L) n
if W/L of NMOS is 5 the W/L ratio of PMOS is 10. The sizing is done in such manner because the mobility of holes is 2times less than mobilty of electrons. This is done so that the resistance offered to current, by PMOS and NMOS remains the same.
It's really nice the way you explain...
If the (W/L)n= 5 then then the (W/L)p should be multiple of 2 to 3.5 of NMOS this is due to mobility the speed of PMOS is lesser than the NMOS ,to increase the speed and they can match each other we keep the (W/L)p PMOS 2 to 3.5 more of NMOS
Hello sir what's the reason behind for not having forward biased... It will flow the current but didn't get the exact reason can you please elaborate
We want a mosfet right , so if we have forward biased pnp instead of it , out purpose of having only mosfet will defeat, in logic level it wont work as we wanted to
Thank you ❤
thank you sir 🙏🙏for such great content
plzz upload part 4
To learn this basics razavi sir vedio
yes more then enough