Blocking vs Non-Blocking Verilog Memory Array Behavior

Demonstrates the difference in behavior of blocking vs non-blocking assignment in Verilog (SystemVerilog) when accessing a small memory array.

[@darksoulscodbo688]

beautifully explained, keep up the good work !!

[@AlJay0032]

What happens when blocking and nonblocking assignments are intermixed?

[@matthewwatkins88]

In what way would mixing blocking and non-blocking assignments cause issues?

[@Rajatsxy]

great

[@recurentgamer1142]

5:30 explication is absent...why mem{a}'s old value went to the output?? Why the old ?

[@outlaw03d]

Because both right hand side values were evaluated first, then assignment happened at the end of that always block.

[@dramaqueen9475]

thats literally the whole point of non blocking assignments

[@MA-qz1sd]

good explanation but this digital stuff is depressing I wish I didnt have to rake it for ee