Verilog Module Instantiation & Routing | 30 Days of Verilog Coding | Day 25

[@chanaganinarender1003]

default_nettype none // Disable implicit nets. Reduces some types of bugs.
module top_module(
input wire [15:0] in,
output wire [7:0] out_hi,
output wire [7:0] out_lo);
assign out_hi=in[15:8];
assign out_lo=in[7:0];
endmodule

[@PilatesinSacramento]

Fantastic, Rajdeep! 🤓

[@reeazhasan4906]

OUBT :
Ref. Question : Create a 4-bit wide, 256-to-1 multiplexer. The 256 4-bit inputs are all packed into a single 1024-bit input vector. sel=0 should select bits in[3:0], sel=1 selects bits in[7:4], sel=2 selects bits in[11:8], etc.
module top_module(
input [1023:0] in,
input [7:0] sel,
output [3:0] out );
//assign out = in[sel*4+3:sel*4];
assign out = {in[sel*4+3], in[sel*4+2], in[sel*4+1], in[sel*4+0]};
endmodule
In the above code there are two assign statements . One is commented out and another one is concatenated . When I am executing the commented out one it is showing error but the concatenation on is working fine . Why so ? I am providing the error statements here .
ERROR : sel is not a constant File

[@whyRD]

Yes will see it tomorrow, and try to get the exact issue , will reply back dont worry

[@reeazhasan4906]

@@whyRD Both the assignment statements means exact same thing . Either slicing or concatenation both should give same output . I am not able to comprehend why it is not giving output for slicing method . Thanks for replying . Also what are the restrictions of using begin and end in sequential always blocks ? For for loop there is a necessity to define for block name . Why is that ?

[@NostalgiaT]

what's the use of encoder and decoder?