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11:00 In 3rd example ,there is error in pairing
Thank You...!!!
Nice
In the static 0 Hazard , tau 2 must be delay of AND gate. I have a doubt regarding the delay of NOT and AND gate , as it shown in the timing diagram tau-1 and tau-2 is given as same. Whether this delay is same for all gate
No its not like all gates have same propagation delay. Generally inverter has least propagation delay since it is the basis for all gates in CMOS.
11:00 In 3rd example ,there is error in pairing
Thank You...!!!
Nice
In the static 0 Hazard , tau 2 must be delay of AND gate. I have a doubt regarding the delay of NOT and AND gate , as it shown in the timing diagram tau-1 and tau-2 is given as same. Whether this delay is same for all gate
No its not like all gates have same propagation delay. Generally inverter has least propagation delay since it is the basis for all gates in CMOS.