Sir thanks a lot for the guidence on ADS. The videos helped me in designing and simulation in ADS. Now if i want to get the equivalent RLC circuit of my structure( in my case split ring resonator) and obtain the values of R,L and C can you please provide me the way. Thanks again.
Hi, I have some question. Why choose the Npts =101(at 4:21Frequency plan section, the defult setting is 50). Does the value affect the accuracy of the simunation? Does the Npts as large as better, but cause the time consuming, how to choose the proper value? Thansk!
When you select Adaptive freq sweep it doesn't matter too much as simulation will stop as soon as it finds result convergence and that's why you see (max) marked in Npts section. We give higher enough number to ensure that simulator will keep trying till that number in case there is certain resonance in the structure which might cause more points to be needed. Hope this helps....
First of all, thanks to you for your tutorials. If I have to design a Complimentery split-ring resonator(CSRR), how will I design the ground plane where I have to create the rings by etching the copper layer and then the top surface where I have to make the feed lines (by etching the copper except the feed)? So basically, how to draw layers for the top as well as bottom. Please suggest.
Hello Sir, Whenever I am performing Mom uW simulations at W band frequency, there's a warning shown in log box - 'Port pins are electrically larger above 55 GHz, S-parameters might be unphysical'. What does it mean? Is it something to do with Pin/Ground ratio? or something else?
This is a common message and it happens when the distance between signal & ground i.e. your substrate height or width of the line edge where you apply the port is >lambda/10 of the highest frequency you are analyzing. If it is caused due to the width of the edge where you are connecting port then it will help if you use Edge Pin and define certain edge length instead of using a normal dot pin. If it is happening due to substrate thickness then you need to relook at the dielectric you are using as too much thickness in the substrate will give rise to surface wave propagation that might cause radiation at high frequencies resulting in poorer circuit performance. Consult someone in the Keysight tech support team to gain more insights into this....
@@BhargavaAnurag Thanks for the response. I figured out by performing simulations that problem is due to dielectric parameter and not due to pins. Good point to note.
Hi, I am getting the following warning in the momentum simulation Maximum number of adaptive frequency samples reached! Fitting models not (completely) converged. Consider : - increasing maximum number of sample points. - activating the reuse option. I increased the mesh density cell/wavelength from 20 to 60 and still got the same issue. I have enabled edge mesh "Auto determine mesh width" and transmission line mesh (number of cells in width =5) Is there any way to solve this issue? Thanks!
Increasing mesh density etc won't help. The message simply means the number of points in freq sweep isn't sufficient to cover the freq span for a converged solution which sometimes can happen to very wide freq range with lesser number of points in adaptive sweep type or too much noise in your circuit performance where lot of resonances are seen. You can take help from local Keysight tech support team if you can't resolve it yourself.
Hi Moise, You can always approach Keysight tech support team to provide you necessary details. Let me know what confusions you have and I will try to create a tutorial on the same sometime in future.
@@BhargavaAnurag Whenever I define a port as SMD the simulator complains that the SMD ports should have a positive and negative pins instead of a single positive pin and ground. This makes sense but how does one define the set up required by the simulator? I am curious to see what difference it would make to have a proper SMD ports setting.
@@moisesafarimugisho9633 if you refer to ADS documentation then it should be pretty clear. The SMD port is connected across 2 pins where eventually you would like to connect the SMD part, see this video for help:th-cam.com/video/gFJxg8CWHx0/w-d-xo.html
Sir, I am doing em cosimulation of a power amplifier in ads. When I am setting up the emcosim view I am getting an error as follows: "Polyline edges and/or wires have been found on STRIP layer and will be ignored. " What is it about? I checked the ports location and all of them are in cond layer and ground in cond2 as per my substrate.
Thanks for arranging these tutorial, while following this tutorial when I click on simulate ADS give " Analysis "Solve" (M211006143740) of design check_lib:getting start with layout:layout failed. Consult the Job Manager log for full details. " this error. Can you please guide me on this?
I would like to do a layout simulation for an RF switch. I built a footprint and wrote SNP data on it as you replied (used fixed Artwork). But in the layout view, I have checked 'Differences from Schematic' and can see the message as 'P2.2 and SNP1.3 are disconnected in layout. I can run the EM simulation but the result is far different from the schematic and is not reasonable. What could go wrong in the layout simulation procedure?
Hi Yuchan, Are you performing EM Circuit cosimulation by bringing EM results back to schematic and performing assembly with circuit components or comparing Schematic results directly with EM results?
@@BhargavaAnurag I would like to compare schematic results directly with EM results. (1. Design a schematic 2. Design a pcb layout based on the schematic). The pcb stack up will be just top (circuit) and bottom (GND) layer.
@@yuchansong8725 It looks like you are missing the point that actual component is based on SnP and that's in your schematic design. In layout what you have is only footprint and connecting line so there is no direct comparison here. What you do in EM simulation in these cases is to account for footprint & interconnect line parasitic and then take that result back to schematic, assemble the SnP component and that will need to be compared with original schematic (if there is a need). Schematic and Layout results can be directly compared & makes sense when you have direct representation of all the components in both formats like Microstrip Filters or distributed matching network etc and not when you have SnP file for a component. Hope this clarifies....
Hello Sir, I am still working on this two warnings "The size of the plus pin for S-parameter port 1/2 is electrically large above 5.09992 GHz, S-parameters may become unphysical." and "The distance between the layout pins for port 1/2 is electrically large above 9.56235 GHz, S-parameters may become unphysical.". What should i do for this warning, sir ?. Really need your help.
Hi, The 1st warning due to the edge size where you connected port is quite wide above 5.09GHz so I would recommend to use Edge/Area Pin instead of dot pin. The 2nd warning is due to distance between + & - terminals of a port, this could happen if you are using a thick substrate and simulating till much higher frequency where substrate can be called as THICK. Sometimes it could be that you placed -ve terminal quite far from +ve pin, so consider bring -ve pin closer to the +ve pin. You can work with your local Keysight tech support to get better assistance.
@@BhargavaAnurag Ok, for the 1st warning, it is solved. And then, for 2nd warning, I am still confused with your suggestion. How can I bring -ve terminal/pin closer to the +ve terminal/pin if GND Layer for - GND pin is ?.
Hi. I am using ADS 2023 Update 2. When I run the Momentum simulation I keep getting the error Error: failed to create or lock the working directory "C:\ADS\MySecondLayout_wrk\..." I have tried changing the working directory and checking file permission in Windows and running as Administrator, but none of these resolve the problem. Does any one have any suggestions?
Your tutorials are great!
Thank you very much!
Glad you like them!
Sir thanks a lot for the guidence on ADS. The videos helped me in designing and simulation in ADS. Now if i want to get the equivalent RLC circuit of my structure( in my case split ring resonator) and obtain the values of R,L and C can you please provide me the way. Thanks again.
Please watch Tutorial 21 and you should be able to do it easily.
Hi, I have some question.
Why choose the Npts =101(at 4:21Frequency plan section, the defult setting is 50).
Does the value affect the accuracy of the simunation?
Does the Npts as large as better, but cause the time consuming, how to choose the proper value?
Thansk!
When you select Adaptive freq sweep it doesn't matter too much as simulation will stop as soon as it finds result convergence and that's why you see (max) marked in Npts section. We give higher enough number to ensure that simulator will keep trying till that number in case there is certain resonance in the structure which might cause more points to be needed.
Hope this helps....
First of all, thanks to you for your tutorials. If I have to design a Complimentery split-ring resonator(CSRR), how will I design the ground plane where I have to create the rings by etching the copper layer and then the top surface where I have to make the feed lines (by etching the copper except the feed)? So basically, how to draw layers for the top as well as bottom. Please suggest.
Kindly see the video on Defected Ground on the channel and it should provide all the necessary details to you.
Hello Sir,
Whenever I am performing Mom uW simulations at W band frequency, there's a warning shown in log box - 'Port pins are electrically larger above 55 GHz, S-parameters might be unphysical'. What does it mean? Is it something to do with Pin/Ground ratio? or something else?
This is a common message and it happens when the distance between signal & ground i.e. your substrate height or width of the line edge where you apply the port is >lambda/10 of the highest frequency you are analyzing. If it is caused due to the width of the edge where you are connecting port then it will help if you use Edge Pin and define certain edge length instead of using a normal dot pin. If it is happening due to substrate thickness then you need to relook at the dielectric you are using as too much thickness in the substrate will give rise to surface wave propagation that might cause radiation at high frequencies resulting in poorer circuit performance.
Consult someone in the Keysight tech support team to gain more insights into this....
@@BhargavaAnurag Thanks for the response. I figured out by performing simulations that problem is due to dielectric parameter and not due to pins. Good point to note.
Hi, I am getting the following warning in the momentum simulation
Maximum number of adaptive frequency samples reached!
Fitting models not (completely) converged.
Consider : - increasing maximum number of sample points.
- activating the reuse option.
I increased the mesh density cell/wavelength from 20 to 60 and still got the same issue. I have enabled edge mesh "Auto determine mesh width" and transmission line mesh (number of cells in width =5)
Is there any way to solve this issue?
Thanks!
Increasing mesh density etc won't help. The message simply means the number of points in freq sweep isn't sufficient to cover the freq span for a converged solution which sometimes can happen to very wide freq range with lesser number of points in adaptive sweep type or too much noise in your circuit performance where lot of resonances are seen.
You can take help from local Keysight tech support team if you can't resolve it yourself.
I have used momentum for quite a while now but I still do not know the correct ports settings especially for SMD cap or resistors.
Hi Moise,
You can always approach Keysight tech support team to provide you necessary details. Let me know what confusions you have and I will try to create a tutorial on the same sometime in future.
@@BhargavaAnurag Whenever I define a port as SMD the simulator complains that the SMD ports should have a positive and negative pins instead of a single positive pin and ground. This makes sense but how does one define the set up required by the simulator? I am curious to see what difference it would make to have a proper SMD ports setting.
@@moisesafarimugisho9633 if you refer to ADS documentation then it should be pretty clear. The SMD port is connected across 2 pins where eventually you would like to connect the SMD part, see this video for help:th-cam.com/video/gFJxg8CWHx0/w-d-xo.html
Sir,
I am doing em cosimulation of a power amplifier in ads. When I am setting up the emcosim view I am getting an error as follows:
"Polyline edges and/or wires have been found on STRIP layer and will be ignored. "
What is it about?
I checked the ports location and all of them are in cond layer and ground in cond2 as per my substrate.
This is not an error but a warning and you can ignore these as they represent you have some wires in layout that will be ignored for EM simulations.
@@BhargavaAnurag ok sir
Thanks for arranging these tutorial, while following this tutorial when I click on simulate ADS give
" Analysis "Solve" (M211006143740) of design check_lib:getting start with layout:layout failed.
Consult the Job Manager log for full details.
"
this error. Can you please guide me on this?
Hi Mike,
I am not entirely sure of the root cause of the issue but I would suggest not to have spaces in the name of the cell/layout.
Hey, i have now the same problem. Do you solve this problem mike?
I would like to do a layout simulation for an RF switch. I built a footprint and wrote SNP data on it as you replied (used fixed Artwork). But in the layout view, I have checked 'Differences from Schematic' and can see the message as 'P2.2 and SNP1.3 are disconnected in layout. I can run the EM simulation but the result is far different from the schematic and is not reasonable. What could go wrong in the layout simulation procedure?
Hi Yuchan,
Are you performing EM Circuit cosimulation by bringing EM results back to schematic and performing assembly with circuit components or comparing Schematic results directly with EM results?
@@BhargavaAnurag I would like to compare schematic results directly with EM results. (1. Design a schematic 2. Design a pcb layout based on the schematic). The pcb stack up will be just top (circuit) and bottom (GND) layer.
@@yuchansong8725 It looks like you are missing the point that actual component is based on SnP and that's in your schematic design. In layout what you have is only footprint and connecting line so there is no direct comparison here. What you do in EM simulation in these cases is to account for footprint & interconnect line parasitic and then take that result back to schematic, assemble the SnP component and that will need to be compared with original schematic (if there is a need).
Schematic and Layout results can be directly compared & makes sense when you have direct representation of all the components in both formats like Microstrip Filters or distributed matching network etc and not when you have SnP file for a component.
Hope this clarifies....
Hello Sir, I am still working on this two warnings "The size of the plus pin for S-parameter port 1/2 is electrically large
above 5.09992 GHz, S-parameters may become unphysical." and "The distance between the layout pins for port 1/2 is electrically large
above 9.56235 GHz, S-parameters may become unphysical.". What should i do for this warning, sir ?. Really need your help.
Hi,
The 1st warning due to the edge size where you connected port is quite wide above 5.09GHz so I would recommend to use Edge/Area Pin instead of dot pin.
The 2nd warning is due to distance between + & - terminals of a port, this could happen if you are using a thick substrate and simulating till much higher frequency where substrate can be called as THICK. Sometimes it could be that you placed -ve terminal quite far from +ve pin, so consider bring -ve pin closer to the +ve pin.
You can work with your local Keysight tech support to get better assistance.
@@BhargavaAnurag Ok, for the 1st warning, it is solved. And then, for 2nd warning, I am still confused with your suggestion. How can I bring -ve terminal/pin closer to the +ve terminal/pin if GND Layer for - GND pin is ?.
Hi. I am using ADS 2023 Update 2. When I run the Momentum simulation I keep getting the error Error: failed to create or lock the working directory "C:\ADS\MySecondLayout_wrk\..."
I have tried changing the working directory and checking file permission in Windows and running as Administrator, but none of these resolve the problem.
Does any one have any suggestions?
I re-formated my PC and re-installed ADS and this fixed the problem.
Thanks for confirmation
great tnx