These lectures were a wonderful combination of nitty-gritty and big picture. They were truly entertaining! If I had had this conversation with this guy over a nice dinner I would have felt very very special. Thanks!
MEBDW has the potential to be awesome for ASICs. Assuming a DR where all the fixed mask litho is a fixed template, and the dicing and packaging is fixed, a manufacturer could produce 10k different chip layouts for approximately the same cost as a 10k batch of one layout. Already the cost of mask generation has driven many ASIC manufacturers to a one metal custom mask, with the rest of the layers fixed. Here's hoping for the days when you can order custom chips in single digit quantities.
No kidding. So they have a giant chip of useful gluey bits of computer logic and it's cheaper to make sure all of that works, throw away almost all of it, and just connect up what you need? Thats very very cool. Almost like the love child of an eprom based plc and an fpga?
Those phase separating polymers cannot be chemically linked or they won't show differential dissolution. So you need a poly-polymer solution in solvent that phase separates upon removal of the solvent and then shows differential solubility in another solvent. Cool!
I assume the entire die is not uniformly populated with a grating prior to cuts and vias being written or else the grating could also be patterned masklessly with interference lithography?
I've never hear of it sounds very good. Could you explain (in a nutshell) how maskless interference lithography is supposed to work? Are there any downsides in terms of NA, wavelength or k1 facto? Are you still able to create different pupils to optimize imaging?
These lectures were a wonderful combination of nitty-gritty and big picture.
They were truly entertaining! If I had had this conversation with this guy over a nice dinner I would have felt very very special. Thanks!
MEBDW has the potential to be awesome for ASICs. Assuming a DR where all the fixed mask litho is a fixed template, and the dicing and packaging is fixed, a manufacturer could produce 10k different chip layouts for approximately the same cost as a 10k batch of one layout. Already the cost of mask generation has driven many ASIC manufacturers to a one metal custom mask, with the rest of the layers fixed.
Here's hoping for the days when you can order custom chips in single digit quantities.
No kidding. So they have a giant chip of useful gluey bits of computer logic and it's cheaper to make sure all of that works, throw away almost all of it, and just connect up what you need?
Thats very very cool. Almost like the love child of an eprom based plc and an fpga?
Thanks for posting!
Those phase separating polymers cannot be chemically linked or they won't show differential dissolution.
So you need a poly-polymer solution in solvent that phase separates upon removal of the solvent and then shows differential solubility in another solvent. Cool!
I assume the entire die is not uniformly populated with a grating prior to cuts and vias being written or else the grating could also be patterned masklessly with interference lithography?
Good question. Obviously the answer would be super interesting. Great question!
I've never hear of it sounds very good. Could you explain (in a nutshell) how maskless interference lithography is supposed to work? Are there any downsides in terms of NA, wavelength or k1 facto? Are you still able to create different pupils to optimize imaging?
very good courses!
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