when you dig down into this topic you will find that the hardware devices all the way down each have their own bespoke implementation of the hardware memory model (probably inevitably given how underspecified the hw memory model is) although from the perspective of the software you can almost always collapse all the lower level implementations into a single layer, at least conceptually. spectre/meltdown (and the like) mitigations are the one major exception that I am familiar with - and because some vendors in that chain decline to provide documentation teasing the lower levels apart always involves some degree of hardware reverse engineering in my experience.
when you dig down into this topic you will find that the hardware devices all the way down each have their own bespoke implementation of the hardware memory model (probably inevitably given how underspecified the hw memory model is)
although from the perspective of the software you can almost always collapse all the lower level implementations into a single layer, at least conceptually. spectre/meltdown (and the like) mitigations are the one major exception that I am familiar with - and because some vendors in that chain decline to provide documentation teasing the lower levels apart always involves some degree of hardware reverse engineering in my experience.