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Sir, you mentioned, according to you, if we consider an NMOS as a non-linear transistor, then at linear region, we shall have higher resistance over saturation region. But how is this true? Measuring R = Vds/Ids, we see that in linear region, R = 1/[knVov - knVds/2], which means resistance increases with increasing Vds. Now, at saturation region, the value of R = 2/knVov, which is maximum for linear region. Onwards in saturation region, we see R = 2Vds/knVov², which is higher than that at linear region. Also in this logic, when input is LOW, output should be high; so load is in linear region and its resistance must be pretty low. As input is HIGH, output should be low; in this case we see current is flowing and load is in saturation. So higher resistance should be there for a proper voltage drop to make output Logic 0. Kindly correct me for any mistakes.
In upnext lectures you are explaining about cmos inverter .... Right now I am going through Sung Mo Kang CMOS digital integrated circuit ... In chapter 5 topic 3 they have explained depletion - load nmos interver .... Where they have mentioned Vout < VDD + VT (load) (load transistor is in saturation ) .... How they come up with Vout < VDD + VT (load) ?
I already told you, to see my playlist in sequence and I am sure, you will never get confused with such questions. It cannot be explained by comments here.
Resistor occupies more area when fabrication comes into picture. Instead we opt for depletion mode transistor which can act as a resistance when gate tied to output node thus occupying same area as NMOS transistor.
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"Your dedication to teaching on TH-cam is truly inspiring. I've learned so much from your videos, and it has helped me. Thank you for sharing your knowledge and enthusiasm with the world!"
Your Appreciations, care and share matters a lot to me. #EnginneringLove.
All the subjects playlist of Engineering Funda is available in comment section. Share it with your friends to support us.
Your positive comments motivates me and person like me get boosted by my students feedback. Thanks and welcome 🙏
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Sir make a video of calculation of voltages for depletion load inverter
Sir, you mentioned, according to you, if we consider an NMOS as a non-linear transistor, then at linear region, we shall have higher resistance over saturation region. But how is this true?
Measuring R = Vds/Ids, we see that in linear region, R = 1/[knVov - knVds/2], which means resistance increases with increasing Vds. Now, at saturation region, the value of R = 2/knVov, which is maximum for linear region. Onwards in saturation region, we see R = 2Vds/knVov², which is higher than that at linear region.
Also in this logic, when input is LOW, output should be high; so load is in linear region and its resistance must be pretty low. As input is HIGH, output should be low; in this case we see current is flowing and load is in saturation. So higher resistance should be there for a proper voltage drop to make output Logic 0. Kindly correct me for any mistakes.
Can you make video on equation of depletion load inverter
Can you please explain how you have decided load nmos is in linear region and saturation region ?
For that go through my playlist in sequence and you get it exactly how it is in linear and saturation
In upnext lectures you are explaining about cmos inverter .... Right now I am going through Sung Mo Kang CMOS digital integrated circuit ... In chapter 5 topic 3 they have explained depletion - load nmos interver .... Where they have mentioned Vout < VDD + VT (load) (load transistor is in saturation ) .... How they come up with Vout < VDD + VT (load) ?
I already told you, to see my playlist in sequence and I am sure, you will never get confused with such questions. It cannot be explained by comments here.
@@niharikamodi5540 There (in the book) they have clearly mentioned that the condition corresponds to
Vds,load > Vgs,load - Vt,load - - - - - (1)
Vgs,load = 0
Vdd = Vds,load + Vout (KVL at o/p)
Vds,load= Vdd - Vout - - - - - (2)
Substitute (2) in (1)
Vdd - Vout > 0 - Vt,load
By rearranging
Vdd + Vt,load > Vout
@@junedmg8703 are bhaai bhaai😅
sir, what if we have a pmos driver in the same circuit, please reply sir
Sir I have doubt for enhancement mode I think it have dotted lines...but u are saying dotted lines for depletion
same
Why depletion load inverter layout area is small?
Why ?
Resistor occupies more area when fabrication comes into picture. Instead we opt for depletion mode transistor which can act as a resistance when gate tied to output node thus occupying same area as NMOS transistor.
Sir why Vt of load is always negaitive for dep mosfet?
bhai depletion type hai channel ko deplete karna hai
why there is symbol change for depletion type MOSFET
Thank you sir .
Your positive comments motivates me, Thanks and welcome 🙏
Can u help me in pmos inverter with driver as pmos and load as depletion type nmos?
As we know that nmos is good to pass logic 0 then why when we give logic 0 to gate the nmos act as open switch???
It is as per circuit.
it's only in saturation from VIL up to Vth of the inverter not VIH
Sir graph ko explain bhi karna tha graph to hai hi hamare pass😢
IL IH calculation
can we have this in Hindi?
Nope
@@EngineeringFunda It's okay, no problem at all. Thanks for great videos.
Your positive comments motivates me, Thanks and welcome 🙏