Learn to indicate Hit and Miss in Cache Memory with an example

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This video is on how to indicate Hit and Miss in cache memory. The following question has been taken as example to elaborate the steps for indicating hit and miss in cache memory.
Consider a small direct map cache with 32 blocks where the cache is initially empty. Block size is 16 Bytes. The following memory are referred 0x3E8, 0x3EC,0x3F0, 0x3F4, 0x9F8 and 0x9FC. Design the map addresses to cache blocks and indicate whether hit or miss.
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[@KOUSHIKPALADUGU-ci2ff]

Super explanation I have never come across this type of explanation

[@hooikkgglqqai4286]

thank you so much!! I finally got it. Cảm ơn vì đã giải thích

[@ksaTiGeR2012]

ur an absolute legend ❤ , thank you so much!! I finally got it

[@digitekkeys2024]

Glad you like it.

[@digitekkeys2024]

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Thank you.

[@Er-iu2zx]

Great and quick explanation 🙏🏿🙏🏿 may God bless you

[@digitekkeys2024]

GOD bless you to

[@juubi4110]

thank you very much i hope ill do well in my test today ! god bless you

[@digitekkeys2024]

God bless you to🙂

[@mrdmahesh]

Very good explanation! Thanks!!

[@digitekkeys2024]

Glad you like it. Please subscribe my channel.

[@mrdmahesh]

@@digitekkeys2024 Subscribed!! :)

[@digitekkeys2024]

@@mrdmahesh Thank you. please share with your friends.

[@gianlucasperti4159]

Hi, I have an exercise where sometimes you have to read-access and sometimes to write-access...so I have a question.
If I access in read mode and miss do I have to write the tag? Or just put Miss?
If I access in write mode I have only to write the tag and not to put Hit or Miss?

[@yinebebtariku1617]

helpful and appreciated!

[@digitekkeys2024]

🙏

[@huskymp4754]

how would i find the block address for the addresses 0x3E8, 0x3EC, etc..?

[@cickeachmmas4553]

Tnx ur the best ❤❤

[@digitekkeys2024]

🙏

[@parthasarathimondal6642]

Thanks for explaining..

[@digitekkeys2024]

Glad it was helpful!

[@rusmq1348]

why are the addresses 32 bit? Where does it tell you?

[@digitekkeys2024]

Yes, the question is not clearly telling that address is 32 bit. I have taken it as an example to explain hit and miss in cache memory. That's why I have also explained hit and miss in cache memory for 12 bit address in another video th-cam.com/video/nrJrKw1fjt8/w-d-xo.html

[@myname1484]

Thank you

[@digitekkeys2024]

🙏

[@chubbahubba1167]

Thought the address was 16Bytes and not 32Bits, i'm a little confused

[@missflecha6084]

i love u

[@shoajbahmadi9950]

that was alot of gyros