Thanks for your video! It's very clear! I cannot imagine I just need to take 5 minutes to understand these. My teacher in school just make me confused.
. An application of 256 KB working set sequentially with the following word address stream: 0, 4, 8, 12, 16, 20, 24, 28, 32, . . . Assume a 64 KB direct-mapped cache with a 32-byte block and 32-bit word size. Fill in the blanks (a) The miss rate for the address stream above if the cache is initially empty = (b) Number of compulsory misses = (c) Total number of misses = (d) If prefetching is used with a two-entry stream buffer and also assume that the cache latency is such that a cache block can be loaded before the computation on the previous cache block is completed. Now, the miss rate for the address stream = (e) Can the performance be increased by increasing the size of the cache? (Yes/No) sir solution pls
thank you sir our ppt was not clear and had a very confusing example but your's I understood well.
Have a great learning in CSE
Me learning one the day of exam 😅😂
Good luck!
Hi
Sem to u brw 😅
Same bro 😂😂😂
ive got 6 hours mate :)
Thanks for your video! It's very clear! I cannot imagine I just need to take 5 minutes to understand these. My teacher in school just make me confused.
Thank you
Have a great learning in CSE
Good Explanation Sir !!
Simple, Logical, Attractive 👏👏👏👏👏👏👏
Glad you think so! Thanks for the feedback
brilliant explanation thank you
Thankyou
Super explanation sir👏
Thanks Sandeep
amazing help, thank you! lifesaver
Thank ,simple great explaning
Awesome content
Have a great learning in CSE
Thank you very much
Thank you sir ❤
Thanks 🎉sir
Wow 🤩
Sir please hindi explaination b upload kiya karo na ussme jyaada badhiya aur achhe se samajh aata hai
Dil khus video
💚
Sap landscape video please
doesnt the avg timewill be 0.9*100 +0.1*1000 = 90+100=190 nsec (how did you get 200 ns as an avg access time)?
Yes
Thanks for identifying
. An application of 256 KB working set sequentially with the following word address stream: 0, 4, 8, 12, 16, 20, 24, 28, 32, . . .
Assume a 64 KB direct-mapped cache with a 32-byte block and 32-bit word size. Fill in the blanks
(a) The miss rate for the address stream above if the cache is initially empty =
(b) Number of compulsory misses =
(c) Total number of misses =
(d) If prefetching is used with a two-entry stream buffer and also assume that the cache latency is such that a cache block can be loaded before the computation on the previous cache block is completed. Now, the miss rate for the address stream =
(e) Can the performance be increased by increasing the size of the cache? (Yes/No)
sir solution pls
Cache coherence video please
th-cam.com/video/GMa7_z6ufQI/w-d-xo.html
th-cam.com/video/P4y2D9-WP18/w-d-xo.html
This link is how to avoid cache coherence
Any MESI PROTOCOL video