An Add/Subtract Calculator with an Accelerometer-Based Input demo, EEC 180

This video shows a demonstration of a simple add/subtract calculator implemented using an Altera / Intel DE10-Lite FPGA board by Terasic.
The on-board accelerometer is used to enter two 2’s complement values into a simple calculator which shows the sum and difference on the HEX display in binary-coded decimal (BCD) format. The calculator works as follows: KEY0 resets the board. After reset, LED0 lights up indicating the next press of KEY1 will load the value shown on the Hex displays into a register operand1. The FPGA board is tipped to generate values that typically range between [-500, +500]. After KEY1 is pressed, LED0 turns off and LED1 lights up indicating the next press of KEY1 will lock the value shown on the Hex displays into register operand2. After KEY1 is pressed a second time, the process repeats allowing the user to alternately load operand1 and operand2.
This lab was used in the course EEC 180 at the University of California, Davis, taught by Prof. Bevan Baas.

[@evangelosdimitriadis9245]

Where can I find the VHDL program and Pin planner settings for DE10-Lite, g-sensor?

[@לי-עםחמו]

I want to ask some questions about operating the accelerometer in the DE10-LITE