I have explained the basics of #UART communication in this video. UART stands for Universal Asynchronous Receiver/Transmitter. It is used in #microcontrollers and FPGAs. I have also covered an explanation of the baud rate, UART frame structure, and parity bit. Comment down your answers to the question. LIKE and SHARE the video. SUBSCRIBE to the channel! UART in MSP430: th-cam.com/video/2g9ohxlH3s0/w-d-xo.html UART troubleshooting steps: th-cam.com/video/r-N53fpaJWo/w-d-xo.html
The receiver should sample the signal in its middle (not on the edge). This is because real life electronics aren't perfect, and there may be latency or voltage jumps here and there; so for example a transmitter's voltage level can go from LOW to HIGH, but if it lags by just a few microseconds after the designated time for leading edge arrives, the receiver will actually still see a LOW level signal, which is a mistake. Thus the sampling should be done in the middle.
According to me the signal should be sampled at the edge i.e when transition takes place according to design we can have positive or negative edge detection.
I have explained the basics of #UART communication in this video.
UART stands for Universal Asynchronous Receiver/Transmitter. It is used in #microcontrollers and FPGAs.
I have also covered an explanation of the baud rate, UART frame structure, and parity bit.
Comment down your answers to the question.
LIKE and SHARE the video.
SUBSCRIBE to the channel!
UART in MSP430: th-cam.com/video/2g9ohxlH3s0/w-d-xo.html
UART troubleshooting steps: th-cam.com/video/r-N53fpaJWo/w-d-xo.html
I have finally understood the concept of parity!
Thank you
You are so magically clear! Thanks a lot for this videos on your channel Bina!
You're welcome!!!
Liked the video,
Would like to understand more on parity from your side
The receiver should sample the signal in its middle (not on the edge). This is because real life electronics aren't perfect, and there may be latency or voltage jumps here and there; so for example a transmitter's voltage level can go from LOW to HIGH, but if it lags by just a few microseconds after the designated time for leading edge arrives, the receiver will actually still see a LOW level signal, which is a mistake.
Thus the sampling should be done in the middle.
Thank you!
Very Good
Very useful video 👍
thank you for video , its quality content , subscribed.
Very useful content
Glad it was helpful! Subscribe to the channel for similar content!
Can u do vedio on I2S and DDR interface a
Receiver can sample the bit at rising edge and falling edge.
According to me the signal should be sampled at the edge i.e when transition takes place according to design we can have positive or negative edge detection.
Mam...Can u plz post more videos about protocols like spi i2c
I have uploaded videos on these topics... check this playlist - th-cam.com/play/PLIhKsUwB2-ezJ4YG3GmswGF4kErcGSDHr.html