Electronics Tutorial - 2/3 Driving multiple MOS-FET transistors in parallel
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- เผยแพร่เมื่อ 31 พ.ค. 2024
- #103 In this video I continue looking at driving multiple transistors in parallel, in particular, I look at what makes MOS-FETs special - how this sort of transistor needs to be driven under various conditions. I look at applications both as a linear amplifier and as a switch.
Miniseries:
Ep1 Parallel BJT: • Electronics Tutorial -...
Ep2 Parallel FETs: • Electronics Tutorial -...
Ep3 Series: • Electronics tutorial -...
References:
assets.nexperia.com/documents...
www.irf.com/technical-info/app...
www.infineon.com/dgdl/para.pd...
Datasheets:
www.onsemi.com/pub/Collateral...
www.onsemi.com/pub/Collateral...
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In the past I did many experiment with switching mosfets in parallel. If I remember correctly, transconductance increases due to lower temperature or higher gate voltage. This increase is the main reason of oscillation. Therefore, controlling transconductance or keeping it low will minimize oscillation. Also, differences of transconductance between mosfets causes one turn on faster or slower than others. By the way, I always enjoy your videos
Great and unique video.
I am now living in Iran, and I can not pay money internationally, that is why I am not your patron. But I am planning to move to UBC in Vancouver next year. The very first thing that I will do is considering to become your patron!
By the way, Happy New Year!
I love the professional presentation of your videos. This video is no exception, and very useful to boot. Thank you! :)
Really good video! I really appreciate the depths you get into and how you slowly get us into the details through intuitive paths
One of the best explanation. Thanks man.
Very very informative as always. Great video. Thanks
Nice and organized presentation I learned new things Thank you for taking the time to do this good video.
Thanks! Very informative and clearly explained as usual!
Wow, this was so informative and exciting, thank You!
I thought I uderstand these circuits, but You showed me that there is happening much more. Thanks for your commitment.
Thanks and nice video ... You can continue on this topic to add snubber circuit .... Other suggestions for videos: Single/double and repetitive pulse test with SOA .. Great work as always
A demonstration would be nice but there's quite a lot of (not complicated but annoying) math involved in describing how a snubber works.
@@typedef_ actually the math can be pretty simple with snubbers if you just solve it with a practical circuit
A very good combination is using a snubber with a small gate resistor and ferrite beat.
@@p_mouse8676 A snubber works by converting an underdamped second order system into a critically damped one. The math is "pretty simple" (matching zeroes with poles in a NEVER-ENDING equation) as you said, but it is far from what the usual content of this channel is.
@@typedef_ What I was trying to say, is that you don't need a lot of math to find the right values. Just one simple formula and some measurements.
Very good tutorial ,,and very clear speak.thank you sir...
Excellent insight. Thanks
Foarte tare ! Excellent explained and presented !
Many thanks for the video! [2:00] Interestingly one way to interpret this graph is that 2N7000 works as a voltage-controlled resistor for low Vds. This property is used in audio compressor / AGC circuits. The idea is to build a voltage divider in which on of the "resistors" is controlled by a feedback loop.
Hello Aleksander! Honestly I have seen more often J-Fet type transistors used for this purpose rather than MOS-Fet. Since those work in reverse (you need to apply a bias voltage to stop conduction rather than start it) it might be easier to ensure a balanced feedback loop. I think that J-Fet also has lower noise than MOS-Fet.
Nice video how to find the value of the gate resistor ? Do we use a pull up resistor when we do parallel too and how to find the value for it if yes ?
thanks for the video , but how can we balance the current in the transistors?
Hi
Many thanks for teaching. On dcdc converter, the main problem in paralleling is that the lower vgs mosfef will take all the current for the transition, so all the dynamic losses will fall in that one. Because the plateau will clamp the gate voltage of the higher vgs th mosfets. Can you make an additional video to show the miller capacitance effect, and the vgs plateau, and why multiple gate resistor may help?
Thanks
Subscribed!
Hello again FesZ!
Thank-you for another wonderful electronics video!
I have 2 comments and 2 questions, which follow.
COMMENT 1:
Discrete CMOS power switches, which may consist of thousands of integrated CMOS transistors in parallel, have mostly replaced discrete BJT power switches. This is because current in the BJT must naturally increase with temperature. This increase requires the placement of ballasting resistors between each BJT emitter and ground. By providing negative feedback, the ballasting resistor prevents, at a minimum, excessive heating, and in the worst case, thermal runaway and device failure. Each ballasting resistor will however consume power. On the other hand, negative feedback is naturally built into the CMOS switch, so no ballasting resistors are required.
Why does the current in a BJT increase with temperature, while not so in the CMOS transistor? In the BJT, the current consists of electrons injected from the emitter into the depletion region associated with the emitter-base pn junction. This depletion region is relatively empty of carriers; that’s why it’s called a “depletion region”. As the temperature rises, thermally generated carriers, called “electron hole pairs” (EHPs), are added to the charge flow in the depletion region. Since the concentration of carriers in the depletion region was very low to begin with, the thermally added carriers dominate the flow. The generation of EHPs with temperature is exponential, so the BJT current increases exponentially with temperature.
Most BJT circuits (not just power circuits) will include an emitter resistor to control this rise in current with temperature. In that case, when we use negative feedback to force the current to be constant with temperature, the VBE must fall as the device will produce the same current with less drive. This is where the -2mV/C° rule-of-thumb (on the VBE) comes from.
In CMOS the same exponential growth of thermally generated EHPs takes place in the channel but we don’t see it because the concentration of carriers from the inversion (from channel formation) is massive in comparison to the number of thermally generated EHPs. In other words, the presence of the thermally generated EHPs is masked by the much higher concentration of electrons already in the channel. At the same time, as the temperature rises, the atoms in the silicon crystal will vibrate more widely. These more energetic and extensive vibrations deflect and impede the drift of electrons in the channel, reducing their mobility. As electron mobility in the channel decreases the channel resistivity rises, and the RDS(ON) of the switch increases. Thus for CMOS switches in parallel, if one begins to conduct more than its fair share of current, its RDS(ON) will rise, which will cause its current to come back down. So negative feedback is automatically built into the CMOS power switch.
As another example, the resistivity of elemental (undoped) silicon has a negative temp co (-70,000 ppm/C°). Resistivity is inversely proportional to the product of carrier concentration and mobility. In undoped silicon the carrier concentration is, relatively speaking, very low (this is why undoped silicon has almost no use in semiconductor technology). Since the room temperature carrier concentration is low, when we heat it, the thermally generated EHPs produce a huge increase in carrier concentration. This is the exact opposite of the case in the CMOS channel. The EHP generation is the same in both cases; but in one case it we see it (undoped silicon), and in the other case we don’t (the CMOS channel). The electron mobility in undoped silicon will fall with increasing temperature for the same reason that it falls in the CMOS channel, but this fall is overwhelmed by the exponential increase in carrier concentration. Therefore the net effect on the resistivity of undoped silicon is that it goes DOWN with temperature.
COMMENT 2:
Everything regarding temperature effects for power applications (triode region) and linear applications (saturated region) is spot on. Really nice work!
I would add only that for power switching applications, the CMOS transistor is ideally in the “deep triode” region where VDS is very small. In that case, the square-law equation reduces to
IDS = μCox(W/L)(VGS − VTH)VDS.
In switching applications, we would often have VGS equal to VDD which puts us very much in the negative temp co region for drain current. In other words, the negative temp co on the mobility dominates, and drain current falls as temperature rises.
It was interesting to hear that at the other extreme, say for linear applications where (VGS − VTH) may be small, you might add a source resistor to fight the positive temp co on the drain current in the same way that the emitter resistor is used in a BJT circuit.
QUESTION 1:
I understood you to say that the LC oscillation arises because we have more than one CMOS switch. Wouldn’t there still be an LC oscillation with only one CMOS switch?
What exactly is the parasitic RCL circuit? Taking power to be an AC ground, I see an inductor from drain to ground, a CDG cap from drain to gate, a CGS cap from gate to ground, and the signal-source resistor from gate to ground. Would not this one CMOS switch produce a parasitic LRC circuit?
QUESTION 2:
In textbooks the inductive kick on the drain is eliminated with a diode clamp. The diode is in parallel with the inductor (anode on the drain, cathode on the supply), so the inductive kick is clamped at one diode drop above the positive supply. What are your thoughts on a diode clamp to squash this LC oscillation?
Thank-you for your time and for all your great work! These videos are very interesting and helpful.
Hello David!
Thank you for the insightful comments!
Regarding the questions, I'll try to answer them to the best of my knowledge:
For the first question - indeed, adding gate resistors is recommended even for single mosfets. Your loop is formed between the low impedance supply, the load in the drain, Cdg and the gate drive (again a low impedance circuit); This loop needs to be dampened with a gate resistor. The difference with more than 1 transistor is that, one common mistake is to place a single resistor in the driver, and create a new loop between the transistors (V+ to drain load, Cdg (t1)- Cdg (t2) drain load and back to V+); here we need extra resistors for each transistor to dampen this new loop.
For the second question - the inductor I added was there to simulate a very long wire; if the circuit would actually have an inductive load (like a relay) then of course a diode would be the best option but, if the inductance comes from a wire (the resistive load is somewhere many meters away from the switch) you can't really add a diode without adding again a very long wire in parallel with the first one. So the diode effect would be neglected because it would be conducting in series with another large inductor.
Kind regards,
Fesz
@@FesZElectronics
Hello Fesz,
Thank-you for your reply!
Yes, I did forget that the inductance was only parasitic inductance, and not a load.
The fact that the oscillation is present with only parasitic inductance makes your point even more general and important. Because then this oscillation must be present whenever a drain is connected to a pin. This seems very worthwhile and good to know about, and I thank you for discussing it!
In terms of thinking about the problem, FOR A SINGLE TRANSISTOR, by grounding the signal source and grounding the power supply, what I see is the following: the source impedance Rs is in parallel with Cgs. Then this parallel combination is in series with Cdg. Then ((Rs || Cgs) + Cdg) is in parallel with the inductance on the drain (which, through the grounded supply goes to ground). When we add more transistors, then simple hand analysis is not feasible and the only important thing to know is how to mitigate the problem, which as you have shown, is to dampen the oscillation.
Great stuff!! Thanks !!
David
Fesz you are the best man.. i need your help can you explain to me how to filter high voltage high frequency high current dc 100v+ ... and how to step down that dc voltage to 12v ..i want to use switching mosfet method with transformer thanks
Just a novice hobbiest, is it possible to control the gate resistance with a micro controller with a digital potentio ic ,by getting thermo or current feed back from the mosfets? This i think could even out the the current spread...
I'm building a linear amplifier for 10 meters using a irfp260n and want to run 6 MOSFETs in parallel to possiblely achieve 1000 watts how do I figure the resistor to load share for the gate and can I add a diode across the resistors. this will be used on a 50 ohm load and at 50vdc
GREAT GREAT VIDEO!!! However HELP PLEASE!, to get through it, I have ONE main question: For power FETs in the saturation mode, I have some rated at over 200A@ only ~2.4mOHM. For a situation like you show in the 1st graph, If my Vds is 10v and Rds is, 0.002 Ohm....isn't that 10v/0.002 Ohm = 5000A ???? WHAT AM I MISSING??
THANKS MUCH!!
Awesome
Hello, Maybe you can present ringing mitigation using snubber in a next video. Thanks for your videos.
Maybe because of my poor english,but anyway something is yet missed.
For example :
How i can parallel 3 NPN Mosfets in a such way to decouple the ESR of each transistor to prevent that ESR to heat-up those transistor or transistors which got the lower ESR inside my network chain ???
Please do a video on double pulse test😀.
Hello FesZ! I have a question about LTspice. I' trying to simulate a log potentiometer with a loudness tap (4 pins potentiometer) but i can't find any solution. Could you help me (or made a video ) Thank's a lot
Hello Anton! I tried doing this at some point in the following fashion: T1-R1-a-R2-T2-R3-b-R4-T3; T1,2,3 are the 3 fixed terminals of the potentiometer; R1+R2 = R3+R4 = half pot value(on a linear potentiometer); a and b are connected by switches to the wiper (the variable part of the pot) - if the potentiometer wiper is in the first half its connected to a; else its connected to b; finally the resistor values are calculated based on the wiper position. For a log potentiometers the schematic should be the same but the R1-R4 values are different;
Hope this helps.
@@FesZElectronics Thank's a lot. It works !
Which software he is using to simulate the circuit
I'm using LTspice in all my videos. Its a free circuit simulation software.
@@FesZElectronics thanks a lot dude 😎
You make grwat videos
Super amazing thanks 👍👍
Thank you! Cheers!
Man, thats the best we can get? I mean, the problem is reduced, but not solved by any mean. The oscilations in the best configuration are still ugly.
Due to after your video I experienced enlightenment. I always burned up my parallel mosfets one by one so far but now I figur out Vgs Id graph and they ara relation with heat. They were not share their Id currents as aqual. Tomorrow am gonna try the different gate voltages to share Id as equally.
But I will not pass that I say, you are just talking with your lips, we all ara not native speaker who watch your video. Maybe you can try to open your teeth while you are speaking. So we can easly understand what you say
I tryed but unfortunatly it aint. I used four IRFP460 mosfets as parallel. I checked datasheet and saw the Vgs as 5,75v at the Id-Vgs graphic that equals Id at the all temperature values. I adjusted my Gate voltage of switching as 5.75v. Result, two of them are at the middle, heating up. 1. is 36 - 2. is 74 - 3. is 67 and the last mosfet is 32 celcius at just for 5A Id
dude u need to sleep