@Mountain Eagle Thanks for your feedback. I'm glad you liked it and my video can help you. You're correct, and I accumulated those materials for more than 20 years since I studied clocking, SerDes, and RF systems. I'm happy that I could spend those time helping people now :)
To put it in a short summary, bandwidth shrinking by cascading CTLE stages comes from the shaper roll-off at high frequencies. We can imagine cascading a few stages of low-pass filters with exactly the same 3-dB frequency such as 1Ghz. The loss at 1Ghz of the overall response of cascaded stages will be lower than 3dB. Hence the shrinking of the bandwidth. Please let me know if this intuition is wrong. Thank you very much and I really like your style of presentation!
Hi CC, I really love your video! Could u make a video to describe why we need an attenuator in front of the CTLE? I want to know how the large input swing may impact the linearity of the CTLE. Thank you a lot!!!
Hi, 信達, nice to meet you, and thank you so much for the good suggestions. Sure. I'll make a video to describe why we need an attenuator in front of the CTLE to improve the linearity of the CTLE suffering from a large input swing. Lastly, I'm glad you like my videos and I'm looking forward to receiving your additional feedback. :)
Hi Chen, the formula (in slides) for cascaded stages is not given correctly. It should be BW_total = BW_stage*sqrt[2^(1/n) - 1] . This formula gives the answer of 6GHz from your slides. Kindly confirm.
Thanks for the good catch. You're correct and I apologize for my typo in the equation. I'm thinking about how to revise this video content not misleading others. Again. I appreciate your careful review :)
Hi CC In Cascade CTLE condition(Additional Redriver at motherboard), the slope of CTLE may sharp than FR4 frequency response. Is it caused over boosting in this case?
Hi Nick, thanks for the very good question. The cascade CTLE is just an idea, but not a final implementation. We need to adjust the zero & pole response in each stage to avoid the over boosting you mentioned. Thanks for the feedback again, and I'll talk about mitigating the over boosting pitfals.
Thank you, CC! I like your video style, very clear. You must have spent a lot of time and energy telling us these details.
@Mountain Eagle Thanks for your feedback. I'm glad you liked it and my video can help you. You're correct, and I accumulated those materials for more than 20 years since I studied clocking, SerDes, and RF systems. I'm happy that I could spend those time helping people now :)
I'm very impressed by your intuitive approach to explaining this circuit.
Hi nitroninetyone, nice to meet you and thank you so much for the feedback. I'm glad the intuitive circuit image helps you. :)😀
To put it in a short summary, bandwidth shrinking by cascading CTLE stages comes from the shaper roll-off at high frequencies. We can imagine cascading a few stages of low-pass filters with exactly the same 3-dB frequency such as 1Ghz. The loss at 1Ghz of the overall response of cascaded stages will be lower than 3dB. Hence the shrinking of the bandwidth. Please let me know if this intuition is wrong. Thank you very much and I really like your style of presentation!
@Zheng Lai Thank you so much for the nice summary. Your intuition makes sense to me. I really appreciate your feedback. 😄
Hi CC, I really love your video! Could u make a video to describe why we need an attenuator in front of the CTLE? I want to know how the large input swing may impact the linearity of the CTLE. Thank you a lot!!!
Hi, 信達, nice to meet you, and thank you so much for the good suggestions. Sure. I'll make a video to describe why we need an attenuator in front of the CTLE to improve the linearity of the CTLE suffering from a large input swing. Lastly, I'm glad you like my videos and I'm looking forward to receiving your additional feedback. :)
Hi Doctor CC, is it possible to talk about CTLE adaptation&tuning in the future video? The criteria to increase or decrease the zeros&poles of CTLE?
Hi HG, thank you so much for the very good suggestions. Yes. I'll do that later. :)
Hi Chen, the formula (in slides) for cascaded stages is not given correctly. It should be BW_total = BW_stage*sqrt[2^(1/n) - 1] . This formula gives the answer of 6GHz from your slides. Kindly confirm.
Thanks for the good catch. You're correct and I apologize for my typo in the equation. I'm thinking about how to revise this video content not misleading others. Again. I appreciate your careful review :)
Very Nice.
Hi Sandeep, nice to meet you, and thanks for the nice words. 😃
Thank you Chen..
Welcome 😊
Hi CC
In Cascade CTLE condition(Additional Redriver at motherboard), the slope of CTLE may sharp than FR4 frequency response.
Is it caused over boosting in this case?
Hi Nick, thanks for the very good question. The cascade CTLE is just an idea, but not a final implementation. We need to adjust the zero & pole response in each stage to avoid the over boosting you mentioned. Thanks for the feedback again, and I'll talk about mitigating the over boosting pitfals.
Hi CC
Thanks for your feedback, I am looking forward to this topic.
@@nickliao7924 You're welcome. Sure. :)