RAM and bus timing - 6502 part 6
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- เผยแพร่เมื่อ 14 ก.พ. 2020
- Schematics, datasheets, kits, and more at eater.net/6502
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Part 1: • “Hello, world” from sc...
Part 2: • How do CPUs read machi...
Part 3: • Assembly language vs. ...
Part 4: • Connecting an LCD to o...
Part 5: • What is a stack and ho...
Part 6: This video!
Part 7: • Subroutine calls, now ...
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"No-one needs more than 16k of memory" Such a great quote to take out of context :)
when you try to do something with an arduino nano with 2k ram you see 16k as unlimited memory.
@oH well,lord! I think it's just that he was shy about making the joke, not knowing if people would get it, and not knowing how appropriate it was to make the quote without naming the source...
@@funnelfpv9435 Try being used to PICs that have less than 1K and you have to bank switch for more than 80 bytes.
@@tylerufen That and the original quote was 640k.
@@Kelan-pn6em And as consequence, the original IBM-PC had addresses 640k < ISA Bus & Peripheral I/O < 1024k mapped and then when more RAM was needed/available all sorts of hoops about paging memory had to be pursued. When they had looked into the crystal ball the designers chose to allow for easier expansion of the peripherals... Woops.
What I learned today is that there's a 30 page manual for a 1" x 1/2" piece of electrified plastic, but it doesn't actually tell You anything. Just gives You a bunch of clues to do Your own detective work.
Its actually a piece of rock encased in plastic.
Special shout out for the graphics overlays. I'm sure that they took a lot of extra time and effort on your part, but I think they really enhance the explanations. Thanks Ben.
Yeah, just one more layer in the Ben Eater toolkit of kick-ass videos. I'm in awe of all of it, not just the subject matter, but the pedagogy. Top flight.
I used to be a bus driver. Was much easier to maintain bus timing when I didn't have to sell tickets to passengers as well as drive the route.
^^
I bet you're glad you didn't have to be precise to the nanosecond though.
welcome to the concept of bus mastering and DMA
@@Elios0000 Direct Money Acceptance?
I used to drive an Airbus.
Interesting how these half-hour videos never seem long enough. Well done
OMG IT WAS 30mn
It felt like 15mn !!!
In the first 10 minutes, the layout is a piece of art itself. The rest is """only""" what ifs during which I heard more than I could have ever thought about.
This really makes you appreciate the engineers and scientists that get your home computers running in the GHz range... And Gb/Tb... And so much more...
It's an iterative process really. They make the chips smaller and more energy efficient, as such they can run them faster without causing meltdowns.
And they make them more tolerant to fluctuations, as well as improve power supply units to maintain a steadier voltage at higher loads.
But we have already reached the physical limit of processor clocks a long time ago. That's why today it's all about parallelisation.
Yeah, any circuit that runs over a few hundred MHz is designed to crazy tolerances, and anything that runs in the GHz range is JFM.
@@WarrenGarabrandt Probably says a lot that we've started running into quantum tunneling issues with our smallest circuits...
...military byproducts...
That's true. However, a single engineer or scientist would not be able to do that, since it requires so much investment and industry problems just to make a single chip. I wish it was possible to do that, though, can you imagine how amazing it would be to just make your own 2.0ghz dual core processor at home ? Surely not comparable to industry standards, that nowadays are like almost 4ghz and at least quad-core, but if that one day could be something that one very intelligent and dedicated person could make by him or herself, that would trully be fucking amazing.
Never before in my life have I thought 32kb of data was a lot until I started watching Ben's videos
Well, 32 thousand characters is quite a bit. Let's assume you wrote that on A4 pages at 3000 characters per page. That's 10 pages and you still have room for an introduction on another page.
And a computer at this low level generally only deals with very simple I/O tasks.
The Apollo 13 spacecraft had 32 KBit of memory (that is, 4 kilobytes) just to put things into perspective.
@@RealCadde and double that size if it was written in 16-bit Unicode for some reason instead of ASCII/UTF8.
@@davidmcgill1000 Or get 36,571 characters if you use 7 bits per character.
And 42,666 characters with 6 bits per character.
And if you ignore upper/lowercase you can even get 51,200 characters with 5 bits per character.
I'm one of those "I had a Commodore 64 when I was 13 types" so it did seem like a lot, back then. It was enough, anyway, for a great deal.
I've been looking at the WDC 65c816, which can bank switch up to 16MB while still having an 8 bit data path: it's basically a 6502 with a 24 bit address space, and wanting to build one....but it occurs to me that a 6502 with just 32KB (or 64KB, in the theoretical max for the C64) could in every way hold a program that could communicate enough with the outside world in order to download new code for execution: in the case of the C64, it did this through modem and disk drives. So even Ben Eater's rudimentary 6502 based computer could, in principle, even with its 8 bit limitation, be stitched into larger scale computing through clustering: 32 KB RAM is way more than you need for a simple supervisory program that can download further assignments over a serial line (network).
Ben's earlier 8 bit computer on breadboards doesn't hand you that, the way his 6502 kit does: the nybble-wide address space sees to that. It would be interesting to see the parallel universe of Ben Eater videos detailing 10 bit computing, 12 bit, etc (each jump allowing double the instruction set as well as double the address space). I'd like to see the video where someone does what Ben did for 8 bit, but with 10 bits, one extra bit each for opcode and address/constant.
@@RealCadde Those Apollo computers were really cleverly programmed, too. They represented all real values as greater than 0 and less than or equal to 1, so you could never, ever, have a divide by zero error: the computer just wasn't capable of representing 0 as a number. I think Margaret Hamilton is the name of the person who figured out how to make it that way: her idea was to make computers that can be mathematically proven to never fail, never to get themselves into a state they can't be gotten out of. It totally worked, too.
I also think all the gates on the Apollo computers were NOR gates, four to a chip: the NOR gate is one of the "universal gates" that you can make any other gate out of. Of course we laugh at those giant (by modern standards) NOR gates and say, we can make much better, but the Apollo people could come right back at us and say, "And how recently have YOU landed people on the Moon?"
Ben: "So in the next video...."
Me: "Nooooooooooooooooo!"
yup, just happened to me too
Can we use another eeprom instead of Ram?
@@zulqarnayeenschaftler9323 No, EEPROM is read-only when it's in the computer.
*_Laughs in the future where he's already done_*
@@zulqarnayeenschaftler9323 EEPROMs write speeds are too slow to be used in a computer. Note that RAMs can read and write with the same speed.
Never ever in my 46 years I encountered anyone who could explain me RAM timing better than this guy.
HBD😀 +- 3 months
"If you're into overclocking, you can give it a try and hope for the best. But in our case we've got other limitations-"
*looks at the breadboard crisscrossed with wires*
... Ya think?
Yeah, breadboard computers are great for learning but terrible at preventing crosstalk.
"Noone needs more than 16k of memory" Lovely quote that aged well
Paul-Stelian Olaru Wasn't it 640k ?
@@blayral Eh, the actual value doesn't matter, in the original quote it did indeed say 640k but it's irrelevant in my view.
@@paulstelian97 xD *looks up modern servers, sees values of several TB* Hmmm, yep, only 640k
@@haraldmbs No one needs more than 640kTB of memory... :o
malloc(100000000000000000000000000);
Ben Eater, your channel helped me understand 4 years of school I went to... I knew everything we studied, but didn't understand it, and your channel made everything just click together.
Almost too good to be true.
Many 8-bit computers simply share their I/O address within the RAM space. Programmers simply know that those address are verboten for program/data use, but conveniently also hold a copy of the I/O registers.
Absolutely love your videos, Ben. I look forward to every one of them!
How does that work with the data bus? If you put an IO address out to read from the IO device, wouldn't the RAM also try to output on the data bus at the same time as the IO device?
@@subDimensionUK afaik those computers usually have more advanced R/W decode logic. Early made by logic gates, later implemented in GAL/PAL ICs. Look up some more advanced homebrew PCs with like 65C816 and focus just on decode logic.
Is verboten really a word English speakers use? That's a germanism I haven't encountered before.
MAYER MAKES yep, I've used it. It means *really* forbidden 😉
@@MAYERMAKES It's not a common word, but I have used it/heard it used.
I just stumbled upon this video and all I can say after over twenty years of professional experience in designing hardware and writing software for it: being able to read and understand datasheets is among the most important skills in my craft. I spend about 20-35% of my time brooding over documentation and not overlooking details is essential for my job. Your videos could be made obligatory training material for any newcomer. Great job!
Your videos are a welcome review for an old guy that doesn't do this stuff full time. For a RAM write it is essential that the address be valid early so that the garbage on the data bus corrupts ONLY the byte that we will ultimately write with valid data anyway and that the data and address remain valid until the 8 memory cells have firmly latched. For a RAM read it is essential that we allow the memory enough time to decode the address and to buffer the data byte onto the data bus before we read it. But it is also essential that we transition from read to write and from write to read while maintaining these two capabilities. This is why RAM timing can seem complex to those who have not considered these three points.
13:29 “we’re interested in reading data right?”
that’s write we are
Great pun
@@snapsecond I agree with that assessment!
Interested in reading data?
I know lots of government agencies that would agree with that
;-)
It's interesting to learn that microprocessors have similar timing limitations as Matt Parker's 10,000 Domino Computer.
Heh, honestly I think that the tolerances on that are tighter, if we scale to the size of the switching devices :P
yeah, but on a nanosecond scale, not on a days scale...
7:57 "Reality is often -complicated- disappointing"
Hence banned in many countries.
Well, if you don't have any expectaions, you won't be dissapointed. Only positiveley surprised!
When half the video is deciphering "helpful" documentation
Because it is highly critical information to understand in order to design with these components.
@@cjay2 I think he's just joking at how convoluted datasheets can be.
@@clonkex Ah! But it was true that everything one needs was in the data book. You just had to study it well. It was all there, you just had to put it all together. But anyone who succeeded became a very knowledgeable designer.
@@cjay2 But why doesn't the datasheet spend more time to explain, say, the timings?
@@VaradMahashabde First, it's not a datasheet. All the earliest 8bit CPU's had User Manuals, where his timing diagrams come from. These were usually several hundred full-size pages, and had full written descriptions of both the Read and Write cycle timings, as well as full descriptions of every instruction in the instruction set of that CPU. I started with the Signetics 2650, an early 8 bit CPU, then graduated to the venerable Z80. Both had complete User Manuals with full descriptions of every aspect of the chip, and both needed to be studied well, in order to use the CPU's properly.
huh.. I finally understand why memory maps are important!! it's literally turning a logical address space into a physical 'this chip needs to store/retrieve this' thing :D
yep and it makes life a whole lot easier
Yes and while I always thought, adresses are holy and only a concern for memory, it is actually a valid thing to hook up logic to them and do all sorts of I/O etc. stuff with certain bus adresses. During our Digital Engineering class we just did it on an FPGA so the internal processor circuitry was essentially virtual, but we had a bunch of hardware hooked up and it was just amazing to figure out how it works. In the end I managed to display a cat gif on an lcd, because that's what technology was made for: cute cat gifs.
@@VulpeculaJoy on the Game Boy, everything is mapped to memory. There's one address you read the buttons from, a few that control the sound generators, one that's hooked up to a shift register for the multiplayer link, a range that contains the attributes of sprite graphics displayed on screen (and that's shared with the GPU so you can only access it at certain times)...
@@renakunisaki Well that's not really true for dedicated GPIO ports. With those you have a bunch of dedicated registers that you adress, and the IO procedure itself is happening completely independent of the bus.
@@VulpeculaJoy This business of doing I/O by mapped memory addresses is one of the things that's key to implementing a 6502 in only 3,514 transistors (or whatever it was). I don't even know how many transistors are in the CPU I'm using to type this.
I am finishing my junior year of college as an electrical engineering major and this series has taught me more practical skills than any one of my proffesors
For anyone wondering why he didn't do anything with the WE signal, if I understood correctly, it's because in the WE signal there isn't time delay, it's just goes up immediately. In the CE signal the problem is that it could be that even though we already changing the address the CE signal still could be low(because the microprocessor didn't change it), but it isn't not the case for the WE signal because it's goes up without delay in the RAM itself ( the RAM chip doesn't wait for a couple nano secends like in CE).
I hope I understood well and hopefully if I didn't I would love to hear the right answer and correction for my saying.
And of course, thank you very much to ben! Amazing and well explained video!
You make this topic very digestible, thank you for your work.
Digestible, Eater, I get it :-)
Almost 20 years ago, before I changed careers into IT, I was a residential and industrial electrician. Was also very obsessed with my wire layout and organization. Neither myself, nor anyone I knew, was as good as the man in this video. His wiring organization, alone, makes him look like an artist!
To my defense, service electrical wiring also requires at least 3 loops of excess. I left 4. Nonetheless, I suspect this man would easily best me on that level too! Very impressive craftsmanship.
Thanks Ben. This helps us appreciate modern systems so much more that operate correctly with amazing time constraints beyond what these classic systems had to deal with. Great technical tutorial for us would-be tinkerers.
In 29:47 Ben said that Write Enable hooked up to the Read/Write on the 6502 isn't necessarily going to go high at least 0 nano seconds before the address becomes invalid. But at 36:50 he says the Write Enable isn't delayed by the worst case 50 nano seconds like the Chip Select is and it will go high on time so the RAM stops writing before the address goes invalid. But the Write Enable Validity is still tied to the address validity like shown in 29:47, at least according to the spec sheet of the processor, isn't it?
I had wondered about that "clock into ram chip select" on the circuit diagram since the start of this project, and now we finally have the answer.
Love the idea of gating the write with the clock! I just don't understand why you chose to gate the chip-select line rather than the write-enable line. Wouldn't that also impact the read cycle and potentially break the data-hold requirements for a read? tCHZ on the memory chip has a minimum of 0ns and since the nand-gate doesn't guarantee a minimum delay either, the total delay before the output of the memory chip goes to high-impedance might be well below the tDHR requirement of the processor. Or am I missing something? :) Great videos, btw! Many thanks for all your hard work!
I was wondering that as well. For what it's worth, it looks like Nintendo used a similar approach to what's shown in the video: console5.com/wiki/Nintendo_NES-001#Schematics
If I'm reading the schematic correctly, the NES main RAM is only enabled (CE) when address 13/14/15 are all low and the clock is high. The RAM's write-enable pin is tied directly to the CPU's RW.
I just got home from a really long day at work and this right here is the highlight of my day :3 Thanks Ben ^.^
You really are a great teacher. Your use of visual aids and the pointed questions really help in understanding something very complex. As soon as you eloquently walked through the problem and ensured I understood, I immediately knew the solution was an inverted AND gate with the clock. You give the audience the feeling of accomplishment and discovery which is something many teachers fail to do.
One of the things I most appreciate about these videos is how you take the time to explain your design decisions; in particular, the fact that often there are various different optimisations to choose from, that compete with each other to some extent. Like choosing to only have 16K of addressable RAM for the sake of making it easier to wire up in hardware: even though at first glance that seems "wasteful", it might actually be more wasteful to spend ages trying to make every last byte of RAM accessible, when we're unlikely to need it all for this project. In many walks of life you have to choose what to optimise for, and the best answer may not be the first optimisation you think of.
You consolidated my belief of you being the best teacher I ever had for digital electronics, when you considered propagation delay by introducing a NAND gate to mitigate the compatibility issue between the processor and the ram. Kudos to you!
the entire playlist is pure treasure! thank you for all your awesome work!
We’re not going to be tested on this, are we?
This is honestly the first one I'll have to re-watch. These timing diagrams are the one thing I've never quite grasped before and I'm sure watching this video a few more times will help with that.
But at the end, the falling edge of the clock is only propagated with a delay of guaranteed 15ns, which is greater than the t_AH of 10ns, so the write would fire even later than without the nand gates....
Exactly! So I don't know if that's 100% guaranteed at all cases the way it's designed
He addresses that at 36:31. The write stops when either CS or WE go high, and WE is not delayed by gates.
@@hxka But WE is not guaranteed to change before the address lines, so still seems like a possible issue.
@@hxka But wasn't the whole point introducing the gates, because we can't be sure WE goes high before any other address line changes? So we made sure CS definitely goes high before anything else changes, which might not be given anymore because of the delay?!
@@F3Ibane Yeah, you're right, he only solved the issue of CS being low too early.
This is the clearest explanation of timing/margin analysis that I've seen.
These videos are amazing. Such high quality, super clear, and so well presented. Ben, you are fantastic, thank you so much.
That summarizes two semesters of Computer Architecture & Microprocessor Design in 38 min video !!
excellent - the last few days I had been thinking about how cpu's and rams' interface with each other - this video is perfectly timed to make my mind wrap around the timing issues!
Makes you appreciate the incredible engineering that must go in modern motherboards. Hundreds of components running at 4000x this speed, all synchronized.
They get really sensitive to trace length at that speed too, which is why layouts are done in software rather than by hand I guess! By hand you could move a set-length piece of tape or string around to keep the length the same, often with a lot of negative space, but software can do many iterations to find decently compact trace spacing.
Nice editing,👍
What a glorious day, a new Ben Eater video has arrived!
This is again an awesome video. I knew a lot of the stuff in the previous ones having hacked my c64 in assembly some 30+ years ago. But here I am learning so much. Keep up the good work. Thanks
40 Minute video to say that we need to hook up a NAND gate to the clock and A15, and I ate up every minute of it. Bravo.
These videos are fascinating to watch just for fun, but they'll be a fantastic resource for anyone who actually builds things for years to come. _impressed emoji_
This is *exactly* the problem I was having with a 65C02 with a 62256 SRAM. I could not see why it would work with a NEC 43256 but not a 62256. Now it is working with either - This video has explained it perfectly - thanks! :)
As always, very good. I'm no expert, but here's a thought or two for anyone reading as belatedly as me:
As the 6502 doesn't see a difference between I/O and memory one could have 'nearly' 32k of RAM simply by ignoring the overlap between the I/O and RAM. In effect when you address your I/O you will also write those values to the RAM at those locations, and the I/O devices will do the same thing. As long as one is aware if this behaviour, and the RAM is fast enough, that overlap won't matter. Being able to 'read' 'unreadable' I/O might be useful.
PS:
If one were so inclined a memory-mapped display could play the same game. If you use a 64k SRAM half of it would be overlaying your ROM. Most of the time that's a waste... until you realise you really only ever read from ROM and write to display RAM. With a bit of wiring jiggery-pokery you get your display RAM effectively for 'free'. As set up with 32K of video memory (or more sensibly 16k with a 16k ROM) without cutting in to system RAM would be a nice thing.
...personally I wouldn't bother - something like a Ti9918a for video is easier to interface and handles all the video/sprite stuff without any real thought required as to how.
20:40 but that is the max set up time at the 14 MHz case. The datasheet shows higher values when running the clock slower though it looks like you'd still have plenty of time to satisfy the RAM.
This is by far the most challenging video in this series. In the future, be sure to keep walking through timing in great detail like you do here -- If I was doing this on my own without your help, I would have been totally lost here. Thanks for explaining things so clearly
This series is absolutely amazing. Beautiful work!
welcome back lord Ben. once again we thank u for ur devine knowledge and explanatory methods. Bless u lord Ben. Amen. 🙏🙏🙏🙏🙏🙏🙏🙏
Your walk-through of the CPU/RAM timing diagrams is genuinely useful. I've been trying to decipher the Atari 2600 timing diagrams and have had great difficulty. It doesn't help that they are hand drawn but none-the-less your description has clarified some points I was unsure about. Thank-you.
Great video Mr. Eater. I hope to someday be on your level, I would have never even thought to look at that, much less be able to find a solution but thanks to you I have an idea on how to go about it. Thank you, this is knowledge I'll always have now.
Thank you very much! This episode perfectly explains timings which I commented about under one of your previous videos.
You keep up the good work. Beautiful work explaining all the details. Made me wiser to these difficult to read timing diagrams.
Such an interesting and useful video going in-depth about timing, nice job, looking forward to the next episode ;)
All your videos makes me very curious to learn...thank u for these videos
Absolutely love these videos.
You're well worth the support 💪👍
Learned a lot
I love your content so much, keep it up!
I really could never make a sense of these timing diagrams.
Now with your explanation I can finally read them. Thank you so much!
This was a lot to process, but it was really eye-opening, as I now understand why we have limitations in overclocking and such, along with the delay factors of even the simplest physical components.
Especially all the fiddling with waitstates to make marginal overclocks behave better!
Been following this series and have been with you 100% until now. But this part is what fried my brain.
Same. I don't understand why the RAM is inacessible sometimes, and nothing on those diagrams makes sense to me.
Really a great video man!
Please keep making such videos.
I am sure that you know this already, but taking the time to use the print outs to walk through your thinking as i would be forced to do is a major part of what makes these videos so good.
Doing this and the step by step approach you take to assembly with testing as you go obviously takes a great deal of time and effort on your part.. I really, really appreciate this! Thank you!
wow... timing is everything.
amazing videos. please more of that!!
Very very very very interesting and joyful. Thank you.
Ok, although it's a 40min video (with some sic! good explain of how to understand those diagrams) that cliffhanger at the end - oh, you teasing us all ...
As a hardware enthusiast i've never got so in-deep into the communication in PCs. It's an amazing lecture.
This is such a great series! Thank you.
cool i am happy this came out faster than the last
I don't know what the improvements were that the Patreon's made were, but thank you: I could not find a single fault with the finished video.
Will this work on my local bus too? The timing is really bad .... I always miss it and have to walk...
Great project! What a pity (at least for me) that part hasn't subtitles and it was hard to fully understand everything, since I'm not native english. I lost some info but I guess I got enough to understand, more or less. This is a wonderful channel, I'm going to build one; I have most of the components here, so I'm just waiting for a couple of ICs to arrive. Thank you so much for your lessons, I now know things that nobody was able to teach as clearly as you did. Thumbs up!
Thanks for all this videos. :-)
You sir, are a wizard!
Excited to build my own system😀 thanks so much for your content, my goal after this system works is to incorporate a controller for stepper drives kind of like Cnc machines I run at work😀 since my career path branched off back in the days of early microprocessors. Keep up with the awesome content👍 You Rock👊👍
I really like your videos. 😍 I would love to see (for example as a next project) how to communicate via the CAN bus (OBD2) in cars.
Fantastic videos. I wish I had these resources when I was doing my computer hardware courses during my CS degree. Thanks!
Excellent video!
the things i learned from your videos are like a gift from god as a computer engineering student thanks ben!
Thank u Ben for this video
Loved it, thanks Ben 👍
That was an excellent video.
I think that the pictures he makes to show the connection between chips are really cool. They make understanding this a lot easier :)
I probably shouldn't have been as excited as I was when I saw "bus timing" at the top of my sub feed
No, you are right to be excited about bus timing, because it is highly critical information to learn, so you can design these systems. Once understood, this stuff is gold.
6:06 "Noone needs more than 16K of memory." :) Love it
I think your videos are awesome, and this topic is extra-great!! yay!
I waited for u r vdeo.
U r teaching is out of world
So useful. Thank you Ben.
You are doing a great job.
I'm a simple man
Ben uploads, I click
im a programmer and have never done any hardware stuff like this but i love these videos!
Very helpful information
Best youtuber, while not being an actual "youtuber"
Fantastic video. This is exactly why it's so hard to get chips to run faster at the same efficiency target.
Such a good series of videos. I wish this was available 20 years ago..
You are really genius. Very good explanation.