Thank you for this excellent video. I've learned how to used the QSPI to implement the SPI with software, but you have shown us how to do it with pure logic. I want to take this code and convert it to VHDL now.
Thank you for these tutorials. I noticed that the DC signal was not toggled to 1 when sending a data byte. Did this result in any errors? Wouldn't the data be interpreted as a command?
This FSM works only if you send exactly 2 bytes through SPI, which is the case for initialization of OLED, fortunately. But what if the number of bytes sent to SPI is varying? You should have use the combined value of spiLoadData and spiDone to handle handshaking and run the case iteratively.
My question is, why not use blocking assignment which ensures execution in order in procedural block, and use delay statement of Verilog #... for 2ms delay.
@@hengzhou4566 1) blocking assignment doesn't synthesize well to sequential circuits, so its a good practice to use only non blockings. 2) #2 is not synthesizable
If you have a single statement undle any control block (like if or while or even always) begin ..end is optional. But if there is more than one statement, it is mandatory
Again a very informative tutorial. One think i don't understand. How the Case(state) statement block became a Case(nextstate) statement block without a problem? th-cam.com/video/iQs3wfZRmxk/w-d-xo.html Thank you very much!
Thank you for this excellent video. I've learned how to used the QSPI to implement the SPI with software, but you have shown us how to do it with pure logic. I want to take this code and convert it to VHDL now.
Thank you a lot bro
You teached me a lot in an easy way so that I could understood
Thank you for these tutorials. I noticed that the DC signal was not toggled to 1 when sending a data byte. Did this result in any errors? Wouldn't the data be interpreted as a command?
Very informative content 👌
This FSM works only if you send exactly 2 bytes through SPI, which is the case for initialization of OLED, fortunately. But what if the number of bytes sent to SPI is varying? You should have use the combined value of spiLoadData and spiDone to handle handshaking and run the case iteratively.
Hello SIr, where can I find the sides please??
how can you make the video on xadc of zed board with program?
Sir upon initialization of the OLED display, why did you not use the data sheet of the OLED directly?
My question is, why not use blocking assignment which ensures execution in order in procedural block, and use delay statement of Verilog #... for 2ms delay.
@@hengzhou4566 1) blocking assignment doesn't synthesize well to sequential circuits, so its a good practice to use only non blockings.
2) #2 is not synthesizable
Sir why do you sometimes write "begin" and "end" keywords for "if" and sometimes don't ?
If you have a single statement undle any control block (like if or while or even always) begin ..end is optional. But if there is more than one statement, it is mandatory
Really good video! Could you please send me the source files? My simulation is the same as yours but idk why it doesn't;t work on the board. Thx!
Source code I have added in the description. But you will have to watch Part 3 also to fully understand it.
@@Vipinkmenon There is an error in source code. Data sheet request VDD is high before display off. Change oled_vdd
Again a very informative tutorial. One think i don't understand. How the Case(state) statement block became a Case(nextstate) statement block without a problem? th-cam.com/video/iQs3wfZRmxk/w-d-xo.html
Thank you very much!