Metal Layer basics in VLSI

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  • เผยแพร่เมื่อ 9 พ.ย. 2024

ความคิดเห็น • 17

  • @bindhur5277
    @bindhur5277 3 ปีที่แล้ว +1

    Thank you for the video!! Great visual representation and explanation!!

  • @naveensilveri1386
    @naveensilveri1386 3 ปีที่แล้ว +1

    Very good concept about routing layers

  • @shaikhaseena7380
    @shaikhaseena7380 2 ปีที่แล้ว +1

    Make a video how we can calculate pitch offer and spacing between metal layers

  • @RamaKrishna-kp7fk
    @RamaKrishna-kp7fk 2 ปีที่แล้ว +1

    Very good concepts 🔥🔥

  • @ujjawalagrawal5195
    @ujjawalagrawal5195 2 ปีที่แล้ว +1

    Great Video Sir !!!

  • @zunaid4664
    @zunaid4664 2 ปีที่แล้ว +1

    Hi ,
    At signal routing stage , during Global routing whether the entire design (CTS completed design) is divided into G-cells or only the availlable routing area?

  • @RamaKrishna-kp7fk
    @RamaKrishna-kp7fk 2 ปีที่แล้ว +1

    Sir i have some questions related to pd..how to reach you to get answers..ur explanation are 🔥🔥🔥

  • @13_jayantkumar78
    @13_jayantkumar78 2 ปีที่แล้ว

    How you are saying that Lower metal layer offer high capacitance and Higher metal layer offer less resistance? Please give explaination on that

  • @tamilselvanselvaraj1798
    @tamilselvanselvaraj1798 2 ปีที่แล้ว +1

    Nice

  • @sardharvankunavath1988
    @sardharvankunavath1988 2 ปีที่แล้ว +1

    if we connect metal1 ,metal2 and metal3 can u compare their resistivity ??/

    • @jairamgouda
      @jairamgouda  2 ปีที่แล้ว +1

      Can you please be a little more specific? I didn't probably get you properly. Do you mean what happens to the total resistance if we use multiple metal layers for a net? Or do you want me to brief about the magnitude of change in resistivity as we go for higher layers?

    • @sardharvankunavath1988
      @sardharvankunavath1988 2 ปีที่แล้ว +1

      @@jairamgouda actually my question if M1 upon M2 like that if we connect what will be the resistivity will varry and which metal have more resistivity and why ??

    • @jairamgouda
      @jairamgouda  2 ปีที่แล้ว +1

      @@sardharvankunavath1988 Yes, I got you. Basically as I have explained in the video, the resistance of the metal M0 is the highest in metal layers and the capacitance is the lowest. Similarly the highest metal used in the chip maybe m5 or M10 or M 18, whatever it is, wil have the highest capacitance and lowest resistance. Why? Because the width of the metals usually increases as we go from M0, M1 to top metal in the design.

    • @sardharvankunavath1988
      @sardharvankunavath1988 2 ปีที่แล้ว +1

      @@jairamgouda okay tqs for ur valuable response