Post-video note: TSMC has moved Backside Power Delivery out of N2P to their A16 node: www.anandtech.com/show/21370/tsmc-2nm-update-n2-in-2025-n2p-loses-bspdn-nanoflex-optimizations
dude, you're talking about the company that refused to innovate at all for a decade, might as well have opened the video with "For the shareholders of j.p. morgan it has never been about the money". im gonna stop this video at 23 seconds, and just not trust you on anything involving intel again.
What about fcga, flip chip grid array? About 20 years ago it turned CPUs upside down. Similar sort of timing when IBM released it copper CMOS tech, which intel rolled out as copper mine. Possibly FCGA just flipped the gates and data lines around.
Until I learned that TSMC has delayed their BSPL I viewed Intel's chances of regaining process leadership as very poor. This actually opens a window of opportunity for them. They will have to deliver consistently for years to come and leverage it to grow their foundary business for it to be more than a blip, but they at least have a chance now.
As an imec researcher I’m seriously impressed by how you made a complex topic easier to comprehend for a layperson. I should learn your techniques when I talk to my bosses 😂. Bravo!!👏
@@jazzochannelare you seriously trying to throw shade at a researcher involved in such cutting edge technology? The balls on some random internet persons!!
@@jazzochannel such a dumb saying. People go to school to learn complex topics and study for a decade+, but yeah lets use a 5 year old kid that has zero clue about the world as some sort of measuring stick 🤣
@@deadales I disagree, humans have a natural tendency to make things more complicated than they need to be. The words used make a huge difference. If the researcher uses a lot of technical vocabulary vs explaining things using normal words, it can convey the same message but one will be understood by a layperson and the other won’t be. If the researcher can’t convey what they’re doing by either way then they probably don’t fully understand the subject. Everything can be explained to a 5 year old by abstracting and splitting it up into smaller pieces.
Well, a lot more people can code with this layer of waste. Good programmers can produce more and bad programmer can produce "good enough". It's a tradeoff and not necessarily a bad one.
@@LupusAries shut up, Windows 11 is not 'spyware", and is not becoming more like just because of an optional feature that is encrypted and local (it's not even work on most 11- supported machines). People like you make good criticism of MS pointless because it gets drowned in an ocean of bad critique and garbage FUD. Also, I find it funny that people like you are mostly saying nothing about the mobile phone - which remains the worst tech wrt privacy to ever exist, and being iOS will not save you.
It’s definitely all the new “features” these applications keep adding, often described as well as the MCAS when the 737 MAX first rolled out if they’re even mentioned at all. The worst of these being Chinese apps, which kept randomly overheating my phone when I still had them installed.
I made a similar comment to this on the video by High Yield about this, but hi! I worked on this. I've been with Intel for nearly a decade and have participated in the bring up of Intel7, Intel4, 20A, and am currently on a next-gen node that can't be named here yet. I did my PhD in semiconductor physics while at Intel, partially sponsored by them, completing in early 2020. I studied the optimization of chip-to-chip power delivery, such as you see with a silicon interposer passing power through to dies on top. Between this video and his, you can get a great overview of these technologies and the sources mentioned at the beginning are some of the best out right now. I'll answer what questions I can here, but I highly recommend taking a peak at my comment on the High Yield video, as I'm well over 100 replies deep in Q&A there.
so my question: since the chips were allready flipped, the machienery bellow and the rest of the silicone up on top, between the heatspreader, is the power delivery now below the heat spreader or is it flipped again? im confused
Backside Power Delivery Network is actually known as BSPDN in the industry. Also, while Imec does incredible research for the industry, the research into BSPDN is a bit nuanced. As you noted, Imec relies on BPR (Buried Power Rail). While this is significantly simpler to manufacture, it provides much less in terms of gains as it requires more space in the cell and still takes up valuable M0 routing space. This also harms voltage droop somewhat. Intel's PowerVia goes with a different approach where the TSVs attach directly to the transistor contacts which means they do not need to rely on BPRs which take up die space and they also do not need to rely on any M0 routing for power at all. It is a more complicated manufacturing method, but it provides much better scaling. Lastly, it is believed that TSMC is attempting to connect TSVs directly to the source and drain of the transistors with its implementation of BSPDN. This provides even greater density, but takes the manufacturing complexity to another level. This is believed to be a big part of the reason why TSMC has delayed their intro into BSPDN... Semiengineering has a nice article about this topic. It is from 2022 though.
Thanks for your comment. As far as Backside Power Delivery Network, I already thought they did this in one form or another, so when this was being covered by everyone it didn't seem like an advancement, rather the direction or road that had to be taken mainly because of signaling issues and scaling.
@@gags730 oh yeah. There have certainly been plenty of white papers and press releases regarding this, especially in recent years. No one has actually implemented it into a high volume manufacturing process node yet though. Intel is expected to be the first.
@@longiusaescius2537 that is a good question, but anyone aside from TSMC can only hope to speculate very roughly. I wouldn't expect significantly more in density and power efficiency though. Perhaps as fabs continue to gain more experience with BSPDN, the gains will continue to improve and this could be where TSMC could demonstrate greater sustained gains. Though as an engineer at Intel, I should probably be hoping they don't 😉
Wow Jon. I’m impressed with how your channel has attracted comments and participation from the folks actually doing the research and development of these topics. Fascinating reading long after your video has ended. Bravo❣️👏🏼
Back in 1985, as a new IC process engineer working for AT&T in their Orlando, FL, CMOS fab, I tried an experiment just for fun (fun being a relative concept) where I thinned a silicon wafer with a Disco backgrinder with increasingly finer grit grinding wheels until the wafer was less than 3 mils thick - approximately the thickness of a piece of paper. Upon releasing the wafer from the vacuum chuck I noticed that the wafer would deform into the shape of a potato chip and would often fracture under the immense stresses introduced by the grinding process. Although the video doesn't adress this issue, I have to assume there is an annealing step included in the procedure used to thin out the wafer not mentioned, else this would not work.
I think a lot has already gone into reducing the internal stresses in the boules the wafers a cut from. 300mm wafers are already only 400 micron before any thinning (so only 4-5x thicker than what you got down to).
I remember reading about a company called Alien Technology making tiny RFID chips. One of their special details was instead of cutting wafers with a saw, they did a backside etch to cut the dies apart. If they are already doing some backside stuff, they could etch through the thin wafer to make it little chunks that are too small to potato-chip. They might even do it twice to cut the chunks and also cut all the way through the die. I'm not sure if this is feasible but maybe they could start with a deeper trench, add a layer of resist, then deposit silicon over it, then the backside metal. They could grind the wafer until it was close, then etch away the remainder until they run in to the resist layer. The last thought I have is what are the thermals like? Theoretically a good connection to power and ground should carry away a lot of the heat and if the packaging is top side BGA, the bottom metal would be on top, almost touching the IHS of a chip which might allow even higher power density.
@@beardoe6874 Wet etching following a grinding operation usually results in the formation of etch pipes as the etchant preferentially etches to relieve stress fractures. There are proprietary tricks we came up with at Bell Labs to overcome this but it doesn't scale up easily to a manufacturable process.
@@bradsalz4084 do you know what Alien Technology was doing? I'm pretty sure they ground and then did the backside etch. I have no idea which processes they had to do beyond the etch but it's a pretty safe bet that they had to add some steps. Any way, I was just spitballing some ideas for how to stress relieve a thin bit of silicon...
Great video, Asianometry! I learned a lot with this video. You touched briefly on this when discussing standard cell geometry, but moving the power to the back of the wafer will also drastically reduce signal routing congestion thus allowing for more transistors per unit area.
Intel has done TSV (thru-silicon Vias) in the past with FOVEROS. That was for signals, but I'm certain the learnings from that paved the way for backside power delivery. As the video points out, there are so many metal layers that power delivery is interfering with signal routing, so the motivation for backside power delivery is clear. For ground, it's probably a trivial procedure because the base silicon is a P-type substrate, which is ground, so a "short" between a VSS TSV and substrate is meaningless. Actually, it's probably desirable. I think the challenge is for power, because the TSV's must NOT make any electrical connection to the P substrate, otherwise it's an electrical short. It's relatively easy for manufacturing test to find failed (either shorted or open) TSV connections for signals, because those failures will prevent signals from going-in, or coming out. But for power delivery, I dont know how you can find individual opens because multiple power pins and buses are grouped together.
@@musaran2 it’s still the material from which all transistors are made. It has very high quality requirements and is grown in special conditions that would probably be difficult to achieve in deposition.
@@musaran2 silicon is very malleable. We can do a lot with it that would require different substrates otherwise. It's one of those "jack of all trades, master of none" materials, in many ways.
We're doing research rn into using graphene nanoribbons as a substitute to silicon for computational medium. Its edge structure can be used as transitor analogs.
Just WOW. The first time I watch your tech video and it just blow me away. Hardcore social topics, history as well as hard tech. This channel is a treasure for all curious minds!
@@TheGreatAtarioimagine how bad it would be if something as sensitive as your light cones were directly exposed to light, you would be constantly picking up obscene faint light and might have to live in a cave
@@TheGreatAtario Not only that, they don't even exit your retina by the edge, they go right through the middle. This leaves a blind spot just off the center of your vision that your brain just edits out.
I enjoy the way you explain in-depth topics in a way anyone can understand without feeling like a dork. I often enjoy the sledge hammer humour for those in the know... You have become my favourite lecturer of all time... I don't even have too get out of bed too learn something. Hehe.
@4:39 i believe it should be bypass capacitors. bypass capacitors are used for quick energy supply (power source bypass) and decoupling capacitors are used for line regulation (noise from a submodule should be decoupled from the rest). although in most application they are treated as the same thing.
I know that some of the Intel guys compare the bring up of a new process to the moon landing. The sheer manpower involved is crazy. My team alone has over a century of combined graduate school education, and we are one ground doing one hyper-specific aspect of the process out of the hundreds of steps.
Silicon construction and PCB construction were already more closely aligned than I thought with the stackup and vias. With this they are closer still. I suppose it's only a matter of time before silicon gets power and ground layers every fourth layer or so. Edit: autocorrect issues
From what I've learned, backside power delivery is supposed to be a huge deal. Basically separating the power and data lines from the ground-up (I believe). It's supposed to greatly increase efficiency, and it is a major uptaking from what it looks like.
So when will it be implemented? I just left a comment about how often we hear about these huge revolutionary ideas and discoveries and then nothing ever comes of it.
@@conor7154 I'm pretty sure it's supposed to be shipping in Intel's arrow lake processors soon, hopefully we will see a big uplift in performance but only time will tell.
@@conor7154Intel 4 had a pilot line where they used Intel 4 process rules but with BSPDN implemented and ran some test chips (just to derisk Intel 20A since Intel is attempting two major process changes at once with 20A). Those have been completed and tested (you can easily find the press release on Google for that). As for I tell 20A and 18A which will bring BSPDN to HVM, 20A is already being used to manufacture next-gen CPUs such as Arrow Lake which is launching later this year. Intel 18A will bring this technology to many customers outside of Intel with Intel Foundry, so in just a couple years you will likely see all the Intel CPUs as well as several other customer chips implementing BSPDN.
@@nicknorthcutt7680I wonder if so much of the stifling of these ideas or them going to waste is because they’re a gamble for such a huge company. Like if it was a tiny company doing small volume they could afford to try new things but when you’re making millions of units is probably too risky to try really new things.
And i am still waiting when they are finally getting result on through-die cooling. Haven't seen any official material on that lately, but the microchannels and through vias seemed to offer quite some cooling capacity. It would certainly increase complexity if you'd need to attach a water-line directly to the die, or have the heatspreader be a large vapourchamber that is connected to the die, but the cooling-performance is outstanding.
3:32 "It comes from the power supply". Uh, minor correction/elaboration. It solely comes from the VRMs. The PSU delivers 3.3V, 5V and 12V, all of which will absolutely fry a modern CPU, so no PSU voltage goes straight to the socket. On modern motherboards the VRM components are a non-trivial part of the total cost. Being able to deliver several hundred amps at very low voltages is costly. But every power domain relating directly to CPU, chipset and memory requires (a lot) less than 3.3V, so a lot of stepping down is required. What remains to be seen is if Intel will manage to execute this time around. Every node since their 10nm (now called Intel 7) has been delayed and underperformed once ready. My gut feeling is that TSMC, who's no stranger to taking leaps of faith, is right in splitting GAA off from BPD to make sure they get each right and have time to thoroughly tune the EDA for each. You can have the best node in the universe, but it will be useless if your engineers (or customers engineers) can't properly design for it.
Deciding if TSMC or Intel's approaches are right solely lands on Intel to deliver. If Intel hits their dates, then Intel was correct and would then be a half step ahead of TSMC. Intel's Directed Self Assembly (DSA) that comes along with 18A could be a big deal on the costs side which will help with adoption.
I wonder if this is a technology that can be back-ported to older process nodes to extend their useful life. Imagine a company adds BSPN and GAAFET to their 16nm node to give it performance and power characteristics equivalent to 8nm, at the price of a 12nm wafer.
It would be great if you cover a research on superconducting computing by imec in one of your future videos. There was an article on this topic in IEEE Spectrum recently.
Actually use the Bosch process at work in dry etch! But we use it for much simpler silicon processes than what Intel does. Super cool to get more information around it
This kinda makes me think of the "Backside Illuminated" image sensor technology that has been implemented in more recent cameras over the last half decade or so.
I have an old Mostek product catalog that describes testing and failure modes. (Old as in 4 kilobit memory chips in the catalog). One failure mode was copper via electromigration. Over time In non linear traces, the current would physically move copper atoms eventually causing open circuits. Now that we are dealing with nanometers instead of microns, I wonder if copper electromigration will become a failure mode. I’m sure the designers are aware of this and probably 10 more things that can create reliability problems.
Oh fer sure, electromigration has been an issue all along, my class in the late '80s included that. Basically keep current density below a certain threshold, so this puts minimum sizes on power traces, though in anything I worked on in 80s (undergrad)-90s(PhD) you were making them large enough to get resistive losses in check that electromigration was not an issue.
"Slap in the face"? Intel is not only the industry leader. It is the innovator. You can half Intel's market share today.. and it would still be higher than the nearest competitor AMD.
@@Katchi_they are carrying a 7 billion operating loss on the foundry business, the revenue in their data center segment (which has been their most reliable cash cow) is also taking a severe hit, they are out of the memory business and ARM architecture is closing the performance gap (it will be interesting to see how Qualcomm ARM chips perform on Windows machines). I own shares of Intel but it'd be foolish not to acknowledge their struggles.
Really informative video, absolutely amazing content! I just have one question, are the data lines connected on top? because im thinking that if we use two of the chip faces how are we gonna efficiently cool it?
Best explanation thus far of this new power delivery design, thank you sir for detailing this design in a comprehensive manner for us non-CPU specific electronic/Electrical engineers! I was excited awhile back when I first heard of this possible change, the benefits going to the 2 possible elements back then, seemed very promising and a major breakthrough, but all still theoretical. Glad to see it being implemented faster than I thought possible.
BSPDN is born to be 3D-IC, the SiGe works as a etch stopping layer. while before that, the upper side of the wafer should already be bonded with the other wafer with high-density interconnects.
I assume that the capacitors on the power rails are on the backside too. Are there any power transistors on the backside? Specifically, transistors for enabling power domains and the transistors for voltage regulation
This is one of the few reasons why I believe Intel is still very much in the fight for the lead when it comes to nodes. Modern nodes aren't all about shrinking anymore, and these kind of innovations are what will keep driving silicon advancements forward.
Yay! Good for them.... another case where competition helped advance things. Didn't you talk a little about BSPD a few episodes ago? I read something about it somewhere.... At some point, seems to me, we'll have to go to optical or virtual or some other medium that transcends the nanometrc scale completely....but what? We've invested trillions in EUV scale lithography, so once the medium changes, what do we do with all that bazillion dollar gear?
Awesome video! Man I would love a phone or watch with even 2x the battery life. Couple that with 60 to 80 watt charging(on the phone) and charging crap will no longer rule my life. Of course Intel isn't phones.. But I would also like to see them reclaim some ground in the server and desktop space. And I'm assuming with this we get more density in that space
Good Feature. i liked it. after that deep walkthrew the streets & Towers of the Chip, think i get a grip on the structure & maybe some names..Finally (-;
You left out the quantum mechanical defect in CMOS. Due to the difference in the mobilities of holes and electrons, there is a transient short from power to ground every clock cycle. That is why power consumption goes up with overclocking.
Have you looked into the genomic sequencing race before? There were multiple super cool technologies, like Ion Semiconductor sequencing, racing to achieve long and cheap reads before Illumina took over the market.
There’s a reason both Intel and TSMC both spend multiple billions of dollars a year in R&D efforts. A lot of work goes into figuring out what works and what doesn’t, and a lot of experimentation trials that effectively get thrown in the trash just so engineers can learn what does and doesn’t work. The end result seems like pure magic to lay people, but there is an enormous amount of hard work that goes into bringing something like this to market in a way that is commercially viable.
How is it underrated? 670k subs for niche topics delivered without fancy graphics is actually really good. Not sure how much larger a market is for these kinds of videos.
No sides taken, sides are irrelevant. This is cool and if it is correct could realistically shrink quite a bit while remaining reliable with yield. Yield determines cost more than anything.
This is completely random but I’d really like to see more videos done on batteries and battery technology. I feel like batteries are the same as cancer treatment, every day we hear about how there’s a new revolutionary discovery that will change everything in a year and then we never hear about it again and nothing changes.
Backside power has been used in GaAs and other III-V semiconductor devices since at least the 1970’s, starting with Bell Labs. The technology was initially introduced to compensate for the poor thermal conductivity of GaAs relative to Si.
The physical design of CPU chips may have to chance soon with the move to double-sided cooling solutions being provided for the physical CPU chip if air-cooling solutions continue to be used as the cooling method. Otherwise, CPU chips could switch to microchannel cooling when the come with a standardized physical connector for applying liquid cooling.
Did I understand it that they fully etch away both the original Silicon wafer, in addition to the SiGe-Layer? (Effectively turning the Carrier Wafer into the actual Wafer, into which the Transistors etc. while be etched etc.)
I don't understand, why can't they just start with buried interconnects as the bottommost layer, then make the buried VIAs on top of it, followed by the buried power rails, and lastly start making transistors on top of them?? Why do they have to make the bottom layers, flip it, then make transistors on the other side, instead of starting with the bottommost layer (buried interconnects) right on the wafer?
One more thing, TSMC is making the BSPDN as a node flavor instead of a spcific node for their planning. This means we may see them backported to previous node.
They can back port it to older process but I think unlikely. Older chips need to be redesigned to use the backside power. Process development and chip development are both very expensive so I would think only new designs will take advantage of this.
![[MV] A leap of faith...ความเชื่อใจครั้งสุดท้าย (From "Petrichor the series")](http://i.ytimg.com/vi/U1piZH2CNXA/mqdefault.jpg)
Post-video note: TSMC has moved Backside Power Delivery out of N2P to their A16 node: www.anandtech.com/show/21370/tsmc-2nm-update-n2-in-2025-n2p-loses-bspdn-nanoflex-optimizations
Interesting, when is A16 due?
dude, you're talking about the company that refused to innovate at all for a decade, might as well have opened the video with "For the shareholders of j.p. morgan it has never been about the money".
im gonna stop this video at 23 seconds, and just not trust you on anything involving intel again.
What about fcga, flip chip grid array? About 20 years ago it turned CPUs upside down. Similar sort of timing when IBM released it copper CMOS tech, which intel rolled out as copper mine. Possibly FCGA just flipped the gates and data lines around.
Awesome video. This is the type of content I meant when I suggested focusing more on manufacturing process developments.
Until I learned that TSMC has delayed their BSPL I viewed Intel's chances of regaining process leadership as very poor. This actually opens a window of opportunity for them. They will have to deliver consistently for years to come and leverage it to grow their foundary business for it to be more than a blip, but they at least have a chance now.
As an imec researcher I’m seriously impressed by how you made a complex topic easier to comprehend for a layperson. I should learn your techniques when I talk to my bosses 😂. Bravo!!👏
your boss should be shamed.
if you can't explain what you do to a five year old, then you don't know what you do.
@@jazzochannelare you seriously trying to throw shade at a researcher involved in such cutting edge technology? The balls on some random internet persons!!
@@jazzochannel such a dumb saying. People go to school to learn complex topics and study for a decade+, but yeah lets use a 5 year old kid that has zero clue about the world as some sort of measuring stick 🤣
@@deadales
I disagree, humans have a natural tendency to make things more complicated than they need to be.
The words used make a huge difference. If the researcher uses a lot of technical vocabulary vs explaining things using normal words, it can convey the same message but one will be understood by a layperson and the other won’t be.
If the researcher can’t convey what they’re doing by either way then they probably don’t fully understand the subject.
Everything can be explained to a 5 year old by abstracting and splitting it up into smaller pieces.
It's sad that while hardware keeps getting faster and better, the software that is run on it keeps getting more bloated and slower.
How do you sell ever faster and more expensive hardware if the software does not get less efficient and use more horsepower?
And becomes more and more like Spyware.....cough, Windows 11, cough, cough.
Well, a lot more people can code with this layer of waste.
Good programmers can produce more and bad programmer can produce "good enough".
It's a tradeoff and not necessarily a bad one.
@@LupusAries shut up, Windows 11 is not 'spyware", and is not becoming more like just because of an optional feature that is encrypted and local (it's not even work on most 11- supported machines). People like you make good criticism of MS pointless because it gets drowned in an ocean of bad critique and garbage FUD.
Also, I find it funny that people like you are mostly saying nothing about the mobile phone - which remains the worst tech wrt privacy to ever exist, and being iOS will not save you.
It’s definitely all the new “features” these applications keep adding, often described as well as the MCAS when the 737 MAX first rolled out if they’re even mentioned at all. The worst of these being Chinese apps, which kept randomly overheating my phone when I still had them installed.
I made a similar comment to this on the video by High Yield about this, but hi! I worked on this. I've been with Intel for nearly a decade and have participated in the bring up of Intel7, Intel4, 20A, and am currently on a next-gen node that can't be named here yet.
I did my PhD in semiconductor physics while at Intel, partially sponsored by them, completing in early 2020. I studied the optimization of chip-to-chip power delivery, such as you see with a silicon interposer passing power through to dies on top.
Between this video and his, you can get a great overview of these technologies and the sources mentioned at the beginning are some of the best out right now. I'll answer what questions I can here, but I highly recommend taking a peak at my comment on the High Yield video, as I'm well over 100 replies deep in Q&A there.
Let's hope OP sees that comment !
Is moore’s law now undead?
all this research but intel still lagging behind amd 😢
so my question: since the chips were allready flipped, the machienery bellow and the rest of the silicone up on top, between the heatspreader, is the power delivery now below the heat spreader or is it flipped again? im confused
I've heard that the large power VIAs where a good way to transport heat to the surface. Whats happening now?
Backside Power Delivery Network is actually known as BSPDN in the industry. Also, while Imec does incredible research for the industry, the research into BSPDN is a bit nuanced. As you noted, Imec relies on BPR (Buried Power Rail). While this is significantly simpler to manufacture, it provides much less in terms of gains as it requires more space in the cell and still takes up valuable M0 routing space. This also harms voltage droop somewhat.
Intel's PowerVia goes with a different approach where the TSVs attach directly to the transistor contacts which means they do not need to rely on BPRs which take up die space and they also do not need to rely on any M0 routing for power at all. It is a more complicated manufacturing method, but it provides much better scaling. Lastly, it is believed that TSMC is attempting to connect TSVs directly to the source and drain of the transistors with its implementation of BSPDN. This provides even greater density, but takes the manufacturing complexity to another level. This is believed to be a big part of the reason why TSMC has delayed their intro into BSPDN... Semiengineering has a nice article about this topic. It is from 2022 though.
Nerd
Thanks for your comment.
As far as Backside Power Delivery Network, I already thought they did this in one form or another, so when this was being covered by everyone it didn't seem like an advancement, rather the direction or road that had to be taken mainly because of signaling issues and scaling.
@@gags730 oh yeah. There have certainly been plenty of white papers and press releases regarding this, especially in recent years. No one has actually implemented it into a high volume manufacturing process node yet though. Intel is expected to be the first.
Would TSMC gain better than 8% if they succeed?
@@longiusaescius2537 that is a good question, but anyone aside from TSMC can only hope to speculate very roughly. I wouldn't expect significantly more in density and power efficiency though. Perhaps as fabs continue to gain more experience with BSPDN, the gains will continue to improve and this could be where TSMC could demonstrate greater sustained gains.
Though as an engineer at Intel, I should probably be hoping they don't 😉
Waiting at the airport for my flight to Computex and watching a Asianometry video. Can life get any better?
Your video on the subject was already very nice
Hello again! I've got Q&N round 2 up here now lol.
I watched your video on backside power delivery, it was good too
Wow Jon. I’m impressed with how your channel has attracted comments and participation from the folks actually doing the research and development of these topics. Fascinating reading long after your video has ended. Bravo❣️👏🏼
Jeff, you should be ashamed of yourself!
Me and my homies all hate Jeff
@@Longlius we all have a jeff
Jeff is the worst 😢
Hey, I just want to finish Cyberpunk 2077.
I already both identify with, and hate Jeff
Also, bravo Jeff.. you made it bro !
Back in 1985, as a new IC process engineer working for AT&T in their Orlando, FL, CMOS fab, I tried an experiment just for fun (fun being a relative concept) where I thinned a silicon wafer with a Disco backgrinder with increasingly finer grit grinding wheels until the wafer was less than 3 mils thick - approximately the thickness of a piece of paper. Upon releasing the wafer from the vacuum chuck I noticed that the wafer would deform into the shape of a potato chip and would often fracture under the immense stresses introduced by the grinding process. Although the video doesn't adress this issue, I have to assume there is an annealing step included in the procedure used to thin out the wafer not mentioned, else this would not work.
I think a lot has already gone into reducing the internal stresses in the boules the wafers a cut from. 300mm wafers are already only 400 micron before any thinning (so only 4-5x thicker than what you got down to).
I remember reading about a company called Alien Technology making tiny RFID chips. One of their special details was instead of cutting wafers with a saw, they did a backside etch to cut the dies apart.
If they are already doing some backside stuff, they could etch through the thin wafer to make it little chunks that are too small to potato-chip.
They might even do it twice to cut the chunks and also cut all the way through the die.
I'm not sure if this is feasible but maybe they could start with a deeper trench, add a layer of resist, then deposit silicon over it, then the backside metal. They could grind the wafer until it was close, then etch away the remainder until they run in to the resist layer.
The last thought I have is what are the thermals like? Theoretically a good connection to power and ground should carry away a lot of the heat and if the packaging is top side BGA, the bottom metal would be on top, almost touching the IHS of a chip which might allow even higher power density.
That issue has been resolved.
@@beardoe6874 Wet etching following a grinding operation usually results in the formation of etch pipes as the etchant preferentially etches to relieve stress fractures. There are proprietary tricks we came up with at Bell Labs to overcome this but it doesn't scale up easily to a manufacturable process.
@@bradsalz4084 do you know what Alien Technology was doing? I'm pretty sure they ground and then did the backside etch. I have no idea which processes they had to do beyond the etch but it's a pretty safe bet that they had to add some steps.
Any way, I was just spitballing some ideas for how to stress relieve a thin bit of silicon...
Is this really a new breakthrough? I've been backsided by Intel for two decades at this point
Powerbottom delivery
@@keyofdoornarutorscat Intel can be such dicks.
It absolutely is an amazing breakthrough, the question is if it actually comes out remotely on time
@@benc3825 yep, basically renovation of the chip from what I believe. Separating the power and data lines from the ground up.
When possible, I always buy AMD. Even though they did not hire me when they had a chance.
Thanks for not making a single joke about backsides. I know that took restraint.
Ikr 😂
I’m great at backside power delivery 😂
I do not appreciate it.
That's the comments sections's job.
Great video, Asianometry! I learned a lot with this video. You touched briefly on this when discussing standard cell geometry, but moving the power to the back of the wafer will also drastically reduce signal routing congestion thus allowing for more transistors per unit area.
The more I watch your videos the more I realize how chip design is the coolest geometry problem ever.
Intel has done TSV (thru-silicon Vias) in the past with FOVEROS. That was for signals, but I'm certain the learnings from that paved the way for backside power delivery.
As the video points out, there are so many metal layers that power delivery is interfering with signal routing, so the motivation for backside power delivery is clear. For ground, it's probably a trivial procedure because the base silicon is a P-type substrate, which is ground, so a "short" between a VSS TSV and substrate is meaningless. Actually, it's probably desirable. I think the challenge is for power, because the TSV's must NOT make any electrical connection to the P substrate, otherwise it's an electrical short.
It's relatively easy for manufacturing test to find failed (either shorted or open) TSV connections for signals, because those failures will prevent signals from going-in, or coming out. But for power delivery, I dont know how you can find individual opens because multiple power pins and buses are grouped together.
TSV is not the critical step in BSPN it is the grinding into precise nanoscopic thickness.
It’s ridiculous how little of the original wafer is left…
Looks like it will eventually be replaced by some layer deposition on alternate growth substrate.
Or is it too cheap to bother?
@@musaran2 it’s still the material from which all transistors are made. It has very high quality requirements and is grown in special conditions that would probably be difficult to achieve in deposition.
@@musaran2 silicon is very malleable. We can do a lot with it that would require different substrates otherwise. It's one of those "jack of all trades, master of none" materials, in many ways.
We're doing research rn into using graphene nanoribbons as a substitute to silicon for computational medium. Its edge structure can be used as transitor analogs.
Just WOW. The first time I watch your tech video and it just blow me away. Hardcore social topics, history as well as hard tech. This channel is a treasure for all curious minds!
Ah, so old CMOS before backside wiring would be like if blood vessels were directly in front of the retina.
Blood vessels (and nerves) _are_ directly in front of the retina
@@TheGreatAtarioimagine how bad it would be if something as sensitive as your light cones were directly exposed to light, you would be constantly picking up obscene faint light and might have to live in a cave
@@TheGreatAtario Not only that, they don't even exit your retina by the edge, they go right through the middle. This leaves a blind spot just off the center of your vision that your brain just edits out.
No, it's off to the side. The centre is fine.
No, it's off to the side. The centre is fine.
I enjoy the way you explain in-depth topics in a way anyone can understand without feeling like a dork. I often enjoy the sledge hammer humour for those in the know...
You have become my favourite lecturer of all time... I don't even have too get out of bed too learn something. Hehe.
@4:39 i believe it should be bypass capacitors. bypass capacitors are used for quick energy supply (power source bypass) and decoupling capacitors are used for line regulation (noise from a submodule should be decoupled from the rest). although in most application they are treated as the same thing.
same component, used for the same reason. different description?
semi conductor manufacturing is probably one of the most badass things in the world next to rockets
microchips clears
Rockets are more fun, but the complexity of semiconductors is just insanely higher.
Chips are not rocket science. It's a lot more complicated
I know that some of the Intel guys compare the bring up of a new process to the moon landing. The sheer manpower involved is crazy. My team alone has over a century of combined graduate school education, and we are one ground doing one hyper-specific aspect of the process out of the hundreds of steps.
That is incredible, considering the first microprocessor was designed by one man.
Thanks again, always appreciate the work that must go into delivering such high quality content
Silicon construction and PCB construction were already more closely aligned than I thought with the stackup and vias. With this they are closer still.
I suppose it's only a matter of time before silicon gets power and ground layers every fourth layer or so.
Edit: autocorrect issues
Waiting for diamond to get incorporated.
Insightful & entertaining as always! Good to meet you last week!
High Yield also made a good video on this.
Thanks, didn't know that channel!
I had to wait until Asianometry to explain it to me. Thank you!
From what I've learned, backside power delivery is supposed to be a huge deal. Basically separating the power and data lines from the ground-up (I believe). It's supposed to greatly increase efficiency, and it is a major uptaking from what it looks like.
So when will it be implemented? I just left a comment about how often we hear about these huge revolutionary ideas and discoveries and then nothing ever comes of it.
@@conor7154 I'm pretty sure it's supposed to be shipping in Intel's arrow lake processors soon, hopefully we will see a big uplift in performance but only time will tell.
@@conor7154Intel 4 had a pilot line where they used Intel 4 process rules but with BSPDN implemented and ran some test chips (just to derisk Intel 20A since Intel is attempting two major process changes at once with 20A). Those have been completed and tested (you can easily find the press release on Google for that). As for I tell 20A and 18A which will bring BSPDN to HVM, 20A is already being used to manufacture next-gen CPUs such as Arrow Lake which is launching later this year. Intel 18A will bring this technology to many customers outside of Intel with Intel Foundry, so in just a couple years you will likely see all the Intel CPUs as well as several other customer chips implementing BSPDN.
@@nicknorthcutt7680I wonder if so much of the stifling of these ideas or them going to waste is because they’re a gamble for such a huge company. Like if it was a tiny company doing small volume they could afford to try new things but when you’re making millions of units is probably too risky to try really new things.
@@conor7154 Intel claims 18A will be "production ready" in the second half of 2024. They do, however, have a track record of being late.
I only have immature comments about the video title.
Excellent video with expert commentary, as always. Thank you.
And i am still waiting when they are finally getting result on through-die cooling. Haven't seen any official material on that lately, but the microchannels and through vias seemed to offer quite some cooling capacity. It would certainly increase complexity if you'd need to attach a water-line directly to the die, or have the heatspreader be a large vapourchamber that is connected to the die, but the cooling-performance is outstanding.
3:32 "It comes from the power supply". Uh, minor correction/elaboration. It solely comes from the VRMs. The PSU delivers 3.3V, 5V and 12V, all of which will absolutely fry a modern CPU, so no PSU voltage goes straight to the socket. On modern motherboards the VRM components are a non-trivial part of the total cost. Being able to deliver several hundred amps at very low voltages is costly. But every power domain relating directly to CPU, chipset and memory requires (a lot) less than 3.3V, so a lot of stepping down is required.
What remains to be seen is if Intel will manage to execute this time around. Every node since their 10nm (now called Intel 7) has been delayed and underperformed once ready. My gut feeling is that TSMC, who's no stranger to taking leaps of faith, is right in splitting GAA off from BPD to make sure they get each right and have time to thoroughly tune the EDA for each. You can have the best node in the universe, but it will be useless if your engineers (or customers engineers) can't properly design for it.
Deciding if TSMC or Intel's approaches are right solely lands on Intel to deliver. If Intel hits their dates, then Intel was correct and would then be a half step ahead of TSMC. Intel's Directed Self Assembly (DSA) that comes along with 18A could be a big deal on the costs side which will help with adoption.
Should have kept watching, VRMs are covered from 4:14 ;)
Kudos for the Hack Wilson shout-out. Deep cut, right there.
Excellent flic. Well researched, well explained and well delivered. Thank you.
I guess transistors were switches all along
Here to learn, and I did. Thanks for a clearly and logically explained video.
I wonder if this is a technology that can be back-ported to older process nodes to extend their useful life.
Imagine a company adds BSPN and GAAFET to their 16nm node to give it performance and power characteristics equivalent to 8nm, at the price of a 12nm wafer.
Please keep having fun and use what ever images you want. Your videos are entertaining.
"Backside Power Delivery"
Is that like the sun shining out of my butt or something?
I think it's more about where you plug the charger in...
Sounds conceptually correct and directionally wrong. Sun shining on butt.
into, think like a laser beam focused on the pink rosebud, or a big magnifying glass focusing the sun on it.
It would be great if you cover a research on superconducting computing by imec in one of your future videos. There was an article on this topic in IEEE Spectrum recently.
Actually use the Bosch process at work in dry etch! But we use it for much simpler silicon processes than what Intel does. Super cool to get more information around it
This kinda makes me think of the "Backside Illuminated" image sensor technology that has been implemented in more recent cameras over the last half decade or so.
Oh, well I guess I should have just waited til 13:20 , lol.
Thanks for the information. Love this channel!
I have an old Mostek product catalog that describes testing and failure modes. (Old as in 4 kilobit memory chips in the catalog). One failure mode was copper via electromigration. Over time In non linear traces, the current would physically move copper atoms eventually causing open circuits. Now that we are dealing with nanometers instead of microns, I wonder if copper electromigration will become a failure mode. I’m sure the designers are aware of this and probably 10 more things that can create reliability problems.
Oh fer sure, electromigration has been an issue all along, my class in the late '80s included that. Basically keep current density below a certain threshold, so this puts minimum sizes on power traces, though in anything I worked on in 80s (undergrad)-90s(PhD) you were making them large enough to get resistive losses in check that electromigration was not an issue.
It feels off to hear praise for Intel in TH-cam these days, I hope Pat can bring the company back on track after their much needed slap in the face.
"Slap in the face"? Intel is not only the industry leader. It is the innovator. You can half Intel's market share today.. and it would still be higher than the nearest competitor AMD.
@@Katchi_they are carrying a 7 billion operating loss on the foundry business, the revenue in their data center segment (which has been their most reliable cash cow) is also taking a severe hit, they are out of the memory business and ARM architecture is closing the performance gap (it will be interesting to see how Qualcomm ARM chips perform on Windows machines). I own shares of Intel but it'd be foolish not to acknowledge their struggles.
Roommate Jeff is my spirit animal
Thanks for the shout out
wow, that dam looks very familiar to the dam in my home city, which also happens to be the biggest on the Balkans
Really informative video, absolutely amazing content!
I just have one question, are the data lines connected on top? because im thinking that if we use two of the chip faces how are we gonna efficiently cool it?
Best explanation thus far of this new power delivery design, thank you sir for detailing this design in a comprehensive manner for us non-CPU specific electronic/Electrical engineers! I was excited awhile back when I first heard of this possible change, the benefits going to the 2 possible elements back then, seemed very promising and a major breakthrough, but all still theoretical. Glad to see it being implemented faster than I thought possible.
BSPDN is born to be 3D-IC, the SiGe works as a etch stopping layer. while before that, the upper side of the wafer should already be bonded with the other wafer with high-density interconnects.
I assume that the capacitors on the power rails are on the backside too. Are there any power transistors on the backside? Specifically, transistors for enabling power domains and the transistors for voltage regulation
Wow that geometry that you made has a optical illusion on it.
The lines never look completely straight, they always look off angle by a bit.
You're having a stroke
This is one of the few reasons why I believe Intel is still very much in the fight for the lead when it comes to nodes. Modern nodes aren't all about shrinking anymore, and these kind of innovations are what will keep driving silicon advancements forward.
BSPN>ESPN man I love this channel
Video begins at 8:19
You mean 0:00
Yay! Good for them.... another case where competition helped advance things.
Didn't you talk a little about BSPD a few episodes ago? I read something about it somewhere....
At some point, seems to me, we'll have to go to optical or virtual or some other medium that transcends the nanometrc scale completely....but what? We've invested trillions in EUV scale lithography, so once the medium changes, what do we do with all that bazillion dollar gear?
Awesome video! Man I would love a phone or watch with even 2x the battery life. Couple that with 60 to 80 watt charging(on the phone) and charging crap will no longer rule my life. Of course Intel isn't phones.. But I would also like to see them reclaim some ground in the server and desktop space. And I'm assuming with this we get more density in that space
Another excellent talk!
I get a feeling Jeff is a real person 6:10 . Haven't heard that much passion before
Good Feature. i liked it.
after that deep walkthrew the streets & Towers of the Chip, think i get a grip on the structure & maybe some names..Finally (-;
4:40 you have it other way.. Inductance resists the raise of voltage, the capacitor acts as a buffer.
Neat!
I clicked this faster than a reflex benchmark test.
This was cracking. Keep it up. (Unless you need a break!)
I could really go for some backside power delivery rn 😩
should have called it back door power delivery ngl
I need it delivered so hard
Gay
Same
I got u 😂😂😂😂😂
You left out the quantum mechanical defect in CMOS. Due to the difference in the mobilities of holes and electrons, there is a transient short from power to ground every clock cycle. That is why power consumption goes up with overclocking.
Have you looked into the genomic sequencing race before? There were multiple super cool technologies, like Ion Semiconductor sequencing, racing to achieve long and cheap reads before Illumina took over the market.
Sounds like its going to be a pain in the arse to implement this.
There’s a reason both Intel and TSMC both spend multiple billions of dollars a year in R&D efforts. A lot of work goes into figuring out what works and what doesn’t, and a lot of experimentation trials that effectively get thrown in the trash just so engineers can learn what does and doesn’t work.
The end result seems like pure magic to lay people, but there is an enormous amount of hard work that goes into bringing something like this to market in a way that is commercially viable.
This channel is massivelly underrated, and forgive my badly writen englisch! Greetings from Flanders, keep up the good work!
How is it underrated? 670k subs for niche topics delivered without fancy graphics is actually really good.
Not sure how much larger a market is for these kinds of videos.
BSPN
do dooo dododo 🎶
BSPN
do dodo do 🎶
I'm still bummed they rejected my job application 36 years ago after I completed my PhD. Bummer.
No sides taken, sides are irrelevant. This is cool and if it is correct could realistically shrink quite a bit while remaining reliable with yield. Yield determines cost more than anything.
Dammit, Jeff!
PowerVIA will be the catalyst that revives the Intel kingdom and saves American semiconductor manufacturing.
This is completely random but I’d really like to see more videos done on batteries and battery technology. I feel like batteries are the same as cancer treatment, every day we hear about how there’s a new revolutionary discovery that will change everything in a year and then we never hear about it again and nothing changes.
It's much like politics in that way..... ¯\_ಠ_ಠ_/¯
Backside power has been used in GaAs and other III-V semiconductor devices since at least the 1970’s, starting with Bell Labs. The technology was initially introduced to compensate for the poor thermal conductivity of GaAs relative to Si.
Amazing explainer!
The physical design of CPU chips may have to chance soon with the move to double-sided cooling solutions being provided for the physical CPU chip if air-cooling solutions continue to be used as the cooling method. Otherwise, CPU chips could switch to microchannel cooling when the come with a standardized physical connector for applying liquid cooling.
Did I understand it that they fully etch away both the original Silicon wafer, in addition to the SiGe-Layer?
(Effectively turning the Carrier Wafer into the actual Wafer, into which the Transistors etc. while be etched etc.)
So complex these things we use everyday and take for granted.
your puns are on point, luv from Taipei>
Always low voltage afaik? 12v comes into motherboard and is stepped down to close to 1v but a ton of amps before entering cpu
3.3 for the CPU
Wake up babe Asianometry just dropped a new video
Shoutouts to Jeff, my dude
Humans can do amazing things. Thank you for the video.
Looking forward to N2P with Zen 8 in 2028! The only thing is that it seems like it will be nearly the same as 18A, with both having a 3nm I/O Die.
I hope Jeff is ok.
we are getting close stacked silicon chips!
Gonna see it in action soon come,
this is the content i came here for!
I wanna know about Jeff! (j/k. Really fascinating video. Thank you for posting this.
cornered Intel is going to be interesting as they used to innovative a lot, their software team is also always amazing (amd still suck in this)
As a frequent user of Intel Graphics Control Centre, no, their software ain't amazing.
Computex is going te be interesting :)
This is why I love the semiconductor industry, it's like they're constantly on a mission to the moon.
Jeff - we remember! ;)
I couldn't tell you how many times I've tried to avoid power delivery to my backside
I don't understand, why can't they just start with buried interconnects as the bottommost layer, then make the buried VIAs on top of it, followed by the buried power rails, and lastly start making transistors on top of them?? Why do they have to make the bottom layers, flip it, then make transistors on the other side, instead of starting with the bottommost layer (buried interconnects) right on the wafer?
One more thing, TSMC is making the BSPDN as a node flavor instead of a spcific node for their planning. This means we may see them backported to previous node.
They can back port it to older process but I think unlikely. Older chips need to be redesigned to use the backside power. Process development and chip development are both very expensive so I would think only new designs will take advantage of this.
Does breaching the reliability wall release the blue smoke?
That sounds like something that would get you in trouble with HR for even discussing at work
I will just come out and say that it takes immense restraint at work already. The number of power-bottom jokes to be made.
I was waiting for this.
3:31 not true. It comes from the motherboard's VRM. The PSU supplies 12V, where have you seen 12V CPUs?