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All the subjects playlist of Engineering Funda is available in comment section. Share it with your friends to support us. Your positive comments motivates me and person like me get boosted by my students feedback. Thanks and welcome 🙏
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Your Appreciations, care and share matters a lot to me. #EnginneringLove. All the subjects playlist of Engineering Funda is available in comment section. Share it with your friends to support us. Your positive comments motivates me and person like me get boosted by my students feedback. Thanks and welcome 🙏
Your positive comments motivates me. Teachers like me just wants positive comment from student. Love from you guys means a lot to me. My goal is to create largest community of engineers in entire globe. Please help me by sharing this playlist with your friends.
Your positive comments motivates me. Teachers like me just wants positive comment from student. Love from you guys means a lot to me. My goal is to create largest community of engineers in entire globe. Please help me by sharing this playlist with your friends.
Your positive comments motivates me, my goal is to create largest community of engineers in entire globe, so please help me for that by sharing this lecture series(playlist) with your friends in social media (watsapp, telegram etc). Thanks and welcome 🙏
Hello: Thank you for your time you put in the videos. I do not understand one thing in your explanation. You do not mention about the clock input signal in the characteristic and the excitation tables. Why?
Characteristics and Excitation does not includes clock signal. It is already considered that with respect to clock there will be transition in any flip flop
Your positive comments motivates me. Teachers like me just wants positive comment from student. Love from you guys means a lot to me. My goal is to create largest community of engineers in entire globe. Please help me by sharing this playlist with your friends.
Your positive comments motivates me. Teachers like me just wants positive comment from student. Love from you guys means a lot to me. My goal is to create largest community of engineers in entire globe. Please help me by sharing this playlist with your friends.
Your positive comments motivates me. Teachers like me just wants positive comment from student. Love from you guys means a lot to me. My goal is to create largest community of engineers in entire globe. Please help me by sharing this playlist with your friends.
Your positive comments motivates me. Teachers like me just wants positive comment from student. Love from you guys means a lot to me. My goal is to create largest community of engineers in entire globe. Please help me by sharing this playlist with your friends.
Your positive comments motivates me, my goal is to create largest community of engineers in entire globe, so please help me for that by sharing this lecture series(playlist) with your friends in social media (watsapp, telegram etc). Thanks and welcome 🙏
@@nimishasreerag6679 it explains next state, for state table transition table and characteristics table i have made saperate video in my Playlist of digital electronics
Thank you sir. Thank you very much for your valuable videos. I am from Kerala. I watched all of your playlist and it is amazing explanation about each topic. God bless you❤
Your positive comments motivates me, my goal is to create largest community of engineers in entire globe, so please help me for that by sharing this lecture series(playlist) with your friends in social media (watsapp, telegram etc). Thanks and welcome 🙏
Your positive comments motivates me. Teachers like me just wants positive comment from student. Love from you guys means a lot to me. My goal is to create largest community of engineers in entire globe. Please help me by sharing this playlist with your friends.
Your positive comments motivates me. Teachers like me just wants positive comment from student. Love from you guys means a lot to me. My goal is to create largest community of engineers in entire globe. Please help me by sharing this playlist with your friends.
Hello everyone :) i believe i how found the explanation to the confusion we are all sitting with. How do we get 0 and 1 as Qn in the truth table's two middle cases.? First, what we must understand is that Qn represents the value of Q in a Nand-SR flip flop. (Q bar) is not represented in this truth table example as it is not relevant in some sence. Next, we must for ourselves try to visualize the Q output. First, let's put: Clock = 1, S=0, R=1. through the first nand gate at the top, (in previous lecture) we take 1 and 0 as inputs and get the S* as 1. For clock and R as inputs we get 1,1 which is 0 (according to our nand-gate truth table. so now we have S* as 1 and R* as 0. If we try to remember the SR-latch walkthrough he did a couple of lectures ago, we know that whenever S is 1, then Q is automatically 0, and when putting that input into the bottom nand-gate with R* then we get 1. so now we have S = 0, and R = 1. However, as mentioned just before, Qn represents the Q, not Q complement. So Qn represnets the Q, which is 0. therefore we put the 0 into the truth table as the value of Qn. For the third case where S = 1 and R = 0, (clock is ofcourse 1) Then the top nand-gate resolves into 1*1 = 0 = S*, and the bottom nand-gate resolves into 1*0 = 1 = R*. so whenever Reset is 1, then (Q compliment) is 0. and when you use 0 as an input for the top NAND-gate with S* then you get 1.. Again, it is very important to remember that Qn represents Q in our Sr flip flop truth table in previous lecture, so (Q compliment ) which is 0, is not included. So basically if you sit down, draw out the SR flip flop sequential circuit with control input as clock, and take clock as 1, and try both: S = 0, R = 1 S = 1, R = 0 Then you will get Q as Q = 0, (Q Bar) = 1 Q = 1, (Q Bar) = 0 But Qn again represnets Q, so the answer for case two would be: Case 2: 0 Case 3: 1. I apologize if i said the same words too many times :) but i don't want to loose anyone :) on beforehand :) thank you :)
NOR gates are not preferred on industrial level because of power consumption and propagation delay issues. NAND gates are easy in comparison with NOR. You can do with NOR but do with NAND instead
You not clear every point I should not understand properly plz sir clear every point becouse we are here to understanding evry point so plz sir improve your explaining skills
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What an explanation sir I had seen 4 to 5 videos of sr ff but can't able to understand but after seeing your video my doubt are vanish. Thank u 💓 sir.
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Thank you so much. Ive been trying to understand characteristic and excitation tables for such a long time but you explained it perfectly.
All the subjects playlist of Engineering Funda is available in comment section. Share it with your friends to support us.
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Thank you sir for the crisp & concise lecture
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At 8:34 next state m 0 &1 do hai as Q & Q^- then why you take 0 only???
Plz tell sir......!!!
At 0 1 next state Qn+1 is 0
At 1 0 next state Qn+1 is 1
Sir how did the Qn change to next states Q(n+1).pz clearify my doubt.
Concept clearing video prof. Thanks 🙏
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I think, the truth table is somehow confusing with the inclusion of clock
sir what is Qn and how you take 0, 1 in next state( QN+1) at 9:05 i didnt get that concept sir
Thank you so much professor !
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I have benefited a lot from this video
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Nice explanation sir....... Thanks a lot sir
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Sir can you please include timing diagrams of all flipflops plzz its a request
Simply super sir. Clearly explained
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13:05 at this why this is S+QnR' and why not S+QnR in the simplified equation
please tell sir i'm really confused about this
Hello: Thank you for your time you put in the videos. I do not understand one thing in your explanation. You do not mention about the clock input signal in the characteristic and the excitation tables. Why?
Characteristics and Excitation does not includes clock signal. It is already considered that with respect to clock there will be transition in any flip flop
In truth table when S=0&R=1 Q should be 0 as it's a reset condition right ? In video it's 1 why?
It is SR latch by NAND, it perfectly explained here so don't worry.
Sir video smjh m aa gaya lkin Qn+1 or karnaugh map nh smjh aaya😭😭
Sir ye engineering m 1st year waale ko pdhna hai kya *karnaugh map* ??🙏
Nice explanation!
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ahhh the accent :3 , Great video
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Very nice explain
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Thank you sooo much sir
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A lot of thank you sir
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great explanation sir
Love and happiness of students is my ultimate goal, God bless you 🙏, keep learning and keep progressing.
Hello sir i have one doubt, why you put the same value in Q and Qn+1 state. Is Qn+1 is the next state of Q??
I have talk about how state will get change with respect to inputs. So different combinations are considered here.
Sir iam tallk about in the case of characteristics table of Q and Qn+1 state. Is it Q and Qn+1 is same?
@@nimishasreerag6679 it explains next state, for state table transition table and characteristics table i have made saperate video in my Playlist of digital electronics
Thank you sir. Thank you very much for your valuable videos. I am from Kerala. I watched all of your playlist and it is amazing explanation about each topic. God bless you❤
Thanq sir🤘
Your positive comments motivates me, my goal is to create largest community of engineers in entire globe, so please help me for that by sharing this lecture series(playlist) with your friends in social media (watsapp, telegram etc). Thanks and welcome 🙏
Well explained sir
Love and happiness of students is my ultimate goal, God bless you 🙏, keep learning and keep progressing.
Thank You
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Sir u used Nand ff, what about Nor ff?
Is SR or RS flip flop is same ? Kindly help me to know sir. this is quite confusing for me
Yup
Tq sir
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Thank u sir
Your welcome dear
sir i can't understand the truth table excitation table..pls help me how to understand it
Truth table is based on change in input to output and Excitation table is based on output change in state to inputs
Sir can you make a video on SR Flip Flop using nor gate
sir please make a pdf notes with what you written in video it will be helpful to us in exams sir
could you do it please !!!!!
It is there on my Android Application Engineering Funda
sir how you put the values of next state in truth table ?
Sir are sr and rs flip flop same? And is the truth table same for both?
Yup
But nobody use the name rs
I scored every mark thanks to you also neso academy @Engineering Funda
sir kindly provide scanned copies pdf of your explanatory notes
it is already uploaded on my application engineering funda
Hello everyone :) i believe i how found the explanation to the confusion we are all sitting with.
How do we get 0 and 1 as Qn in the truth table's two middle cases.?
First, what we must understand is that Qn represents the value of Q in a Nand-SR flip flop.
(Q bar) is not represented in this truth table example as it is not relevant in some sence.
Next, we must for ourselves try to visualize the Q output.
First, let's put:
Clock = 1, S=0, R=1.
through the first nand gate at the top, (in previous lecture) we take 1 and 0 as inputs and get the S* as 1.
For clock and R as inputs we get 1,1 which is 0 (according to our nand-gate truth table.
so now we have S* as 1 and R* as 0.
If we try to remember the SR-latch walkthrough he did a couple of lectures ago,
we know that whenever S is 1, then Q is automatically 0, and when putting that input into the bottom nand-gate with R* then we get 1. so now we have S = 0, and R = 1.
However, as mentioned just before, Qn represents the Q, not Q complement.
So Qn represnets the Q, which is 0. therefore we put the 0 into the truth table as the value of Qn.
For the third case where S = 1 and R = 0, (clock is ofcourse 1)
Then the top nand-gate resolves into 1*1 = 0 = S*, and the bottom nand-gate resolves into
1*0 = 1 = R*. so whenever Reset is 1, then (Q compliment) is 0. and when you use 0 as an input for the top NAND-gate with S* then you get 1..
Again, it is very important to remember that Qn represents Q in our Sr flip flop truth table in previous lecture, so (Q compliment ) which is 0, is not included.
So basically if you sit down, draw out the SR flip flop sequential circuit with control input as clock, and take clock as 1, and try both:
S = 0, R = 1
S = 1, R = 0
Then you will get Q as
Q = 0, (Q Bar) = 1
Q = 1, (Q Bar) = 0
But Qn again represnets Q, so the answer for case two would be:
Case 2: 0
Case 3: 1.
I apologize if i said the same words too many times :) but i don't want to loose anyone :)
on beforehand :) thank you :)
this is damn awesome than video..!!!
Excellent explanation sir..
But i want notes sir
It is there on my Android Application Engineering Funda
Sir please explain timing diagram
You should go more in depth conceptually, it doesn't provide the feel how that circuit works...
whenever you make a video try to add the topics that are related to the sum and not by saying that watch my last video
Okay
sir can we get the notes
From my Android Application Engineering Funda
If we put SR NOR gate ??
NOR gates are not preferred on industrial level because of power consumption and propagation delay issues. NAND gates are easy in comparison with NOR. You can do with NOR but do with NAND instead
Notes of this lecture plz?
Go through my android application engineering funda, link of application is there in description of video.
@@EngineeringFunda i have download ur app,but where are notes of this lecture in that app?
@@m.yaseen7097 go in EC branch >> then go in Digital electronics >> then go in free materials >> then you can get materials as per your need.
Set*
You not clear every point I should not understand properly plz sir clear every point becouse we are here to understanding evry point so plz sir improve your explaining skills
Try to see from first lecture, or the previous one if you are stucking , I think sir explained properly.
What is SR🥲🥲🥲🤭🤭
Set Reset
Your app is not working it's not signing
Sir, can you please help me.
I am working on, this problem will get solved very soon.
Now application is working perfectly fine, I have resolved that issue of log in. You can use all materials free of cost.
@@EngineeringFunda
Thanks for your efforts 😘
Thank you sir for the crisp & concise lecture
You are most welcome