@@mateoslab If you receive this error: "Error (199013): HDL output file name contains a non-existent directory path" try restore defaults to fix it: Simulation -> Simulation Settings -> Restore Defaults ->Save That worked for me!
If you receive this error: "Error (199013): HDL output file name contains a non-existent directory path" try restore defaults to fix it: Simulation -> Simulation Settings -> Restore Defaults ->Save That worked for me!
Make sure you saved the file name correctly. Also it’s possible that you get different results if you are using a different version of quartus from what the tutorial is based upon.
hello ma'am i have some problems when i did this simulation.error is Error (199013): HDL output file name "D:/project/schematic/LUC_Board_Development/simulation/qsim/CPLD/Waveform.vwf" used with --testbench_file option contains a non-existent directory path Error: Quartus Prime EDA Netlist Writer was unsuccessful. 1 error, 1 warning Error: Peak virtual memory: 475 megabytes Error: Processing ended: Fri May 10 08:40:23 2019 Error: Elapsed time: 00:00:03 Error: Total CPU time (on all processors): 00:00:01 Error. i'm using quartus prime lite edition 17.1if you possible can you help me about this problem?thank you
This video was made using an older version of Quartus (I think it was version 15.0). If you are using version 17.0 then follow my other videos on my channel on creating a simulation on ModleSim with SystemVerilog
Mateo Ceballos Querol it is possible that it won’t work if you are using a newer version of Quartus. This video is based on version 15.0. You should be able to download older versions of quartus from Intel’s website. If you are using version 17.0 then follow my other videos that uses SystemVerilog and testbenches
Thanks Rania, excellent stuff.
if anyone's getting an error during simulation (at 3:35) , save the file again as "waveform" and rerun the simulation
Thanks
i did it both ways i get the same error help pls
Thank you, you're a lifesaver!!
@@mateoslab If you receive this error: "Error (199013): HDL output file name contains a non-existent directory path" try restore defaults to fix it:
Simulation -> Simulation Settings -> Restore Defaults ->Save
That worked for me!
tysm
Nice tutorial. Thanks :)
You are awesome.
If you receive this error: "Error (199013): HDL output file name contains a non-existent directory path" try restore defaults to fix it:
Simulation -> Simulation Settings -> Restore Defaults ->Save
That worked for me!
good tutorial my friend
Thank you ma'am
Thaaaaaanksss
Error (suppressible): (vsim-12110) The -novopt option has no effect on this product. -novopt
in Simulation settings, hit "restore defaults" then from the vsim line delete " -novopt"
thanks, legend
I have experiencing error during simulation
I get the error messeage again and again "unable to open Waveform.vwf.vt" . What is it mean?
Make sure you saved the file name correctly. Also it’s possible that you get different results if you are using a different version of quartus from what the tutorial is based upon.
hello ma'am i have some problems when i did this simulation.error is Error (199013): HDL output file name "D:/project/schematic/LUC_Board_Development/simulation/qsim/CPLD/Waveform.vwf" used with --testbench_file option contains a non-existent directory path
Error: Quartus Prime EDA Netlist Writer was unsuccessful. 1 error, 1 warning
Error: Peak virtual memory: 475 megabytes
Error: Processing ended: Fri May 10 08:40:23 2019
Error: Elapsed time: 00:00:03
Error: Total CPU time (on all processors): 00:00:01
Error. i'm using quartus prime lite edition 17.1if you possible can you help me about this problem?thank you
허성진 try saving your file with the name waveform and run the simulation again.
@@raniahussein4974 i have the same problem and it doesn't work
This video was made using an older version of Quartus (I think it was version 15.0). If you are using version 17.0 then follow my other videos on my channel on creating a simulation on ModleSim with SystemVerilog
Mateo Ceballos Querol it is possible that it won’t work if you are using a newer version of Quartus. This video is based on version 15.0. You should be able to download older versions of quartus from Intel’s website. If you are using version 17.0 then follow my other videos that uses SystemVerilog and testbenches
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