Your tutorial is very detailed and helpful to me. But I still don't understand Axi bus code and offset address. Do you have a related course introduction? Thank you very much for your recommendation.
That is a general style in system design. May be you can watch this video to (at least the intro part) to get and idea. th-cam.com/video/Iwpu4FPZqXY/w-d-xo.html
@@TheVipinkmenon I'm sorry for your misunderstanding due to my unclear expression. What I can't understand is the AXI related code in Verilog. For example, why is the offset address of 0x8 the address of merge register? It seems that I didn't see the relevant definition in Verilog. Thank you again for your patience in your busy schedule.
The addresses are defined by the designer at hardware design time. So yes the merge address is defined in Verilog code. From sw perspective addresses will be multiple of 4 since each register is 4bytes wide. The mapping is in Verilog code
Extremely helpful tutorial, sir! How can we translate this design to a 64-bit operation? (Target board: Zybo7z020) The S_AXI_WDATA registers appear to be 4 bytes of data and so to accommodate the 64-bit operation, do we need to split the input into two parts or is there an elegant way to work out this problem?
No. Software is sequential and on a hardware bus there can be only one operation at a time. If AXI4 full interface is used, it can support simulatenous read and write. But from a software point of view it will never happen. Even if standalone supported multi threading (which it doesn't)
Your processor and OS both are 32 bits. So there is no way to write a 64-bit data in ones hot to hardware. Hardware is capable of comparing and merging 2 64-bit numbers on a single clock. But not software. So for each number you will have to write twice. Better to use an asymmetric FIFO to store data (32-bit write width and 64 bits read widths) so that merge operation can be using 64 bits. Again at the output you will need an asymmetric FIFO (64 write and 32 read) from where it will go to processor and it will need 2 reads/data
In FWFT configuration of the FIFO, we have incoming data visible at the output without any latency. As a result, increasing the frequency will be an issue right? (without the pipeline register that corresponds to the latency)
FWFT can be implemented with pipelining and I believe Xilinx has that internal pipeline. The difference from standard FIFO will be the latency for the empty/valid signal to change when a new data is put in the FIFO.
Thanks for this video. It helped me a lot to understand workflow of vivado
You are amazing. Thank you a lot.
Thank you!
hello sir, this course was kind of confusing in the register mapping part in axi controller is there any material I can refer to for that part
Thank you so much
Your tutorial is very detailed and helpful to me. But I still don't understand Axi bus code and offset address. Do you have a related course introduction? Thank you very much for your recommendation.
That is a general style in system design. May be you can watch this video to (at least the intro part) to get and idea. th-cam.com/video/Iwpu4FPZqXY/w-d-xo.html
@@TheVipinkmenon I'm sorry for your misunderstanding due to my unclear expression. What I can't understand is the AXI related code in Verilog. For example, why is the offset address of 0x8 the address of merge register? It seems that I didn't see the relevant definition in Verilog. Thank you again for your patience in your busy schedule.
The addresses are defined by the designer at hardware design time. So yes the merge address is defined in Verilog code. From sw perspective addresses will be multiple of 4 since each register is 4bytes wide. The mapping is in Verilog code
Extremely helpful tutorial, sir! How can we translate this design to a 64-bit operation? (Target board: Zybo7z020)
The S_AXI_WDATA registers appear to be 4 bytes of data and so to accommodate the 64-bit operation, do we need to split the input into two parts or is there an elegant way to work out this problem?
Also, can we have more than one register that the processor can write to (or read from) simultaneously?
No. Software is sequential and on a hardware bus there can be only one operation at a time. If AXI4 full interface is used, it can support simulatenous read and write. But from a software point of view it will never happen. Even if standalone supported multi threading (which it doesn't)
Your processor and OS both are 32 bits. So there is no way to write a 64-bit data in ones hot to hardware. Hardware is capable of comparing and merging 2 64-bit numbers on a single clock. But not software. So for each number you will have to write twice. Better to use an asymmetric FIFO to store data (32-bit write width and 64 bits read widths) so that merge operation can be using 64 bits. Again at the output you will need an asymmetric FIFO (64 write and 32 read) from where it will go to processor and it will need 2 reads/data
@@TheVipinkmenon Understood! Thank you!
In FWFT configuration of the FIFO, we have incoming data visible at the output without any latency. As a result, increasing the frequency will be an issue right? (without the pipeline register that corresponds to the latency)
FWFT can be implemented with pipelining and I believe Xilinx has that internal pipeline. The difference from standard FIFO will be the latency for the empty/valid signal to change when a new data is put in the FIFO.