Dear Sir, Thank you very much for your clarification. However, the PTM site is down and I would like to ask your help where I can get the 7nm cmos technology model. Thank you.
I want to use transmission gate in my design but it is not available as standard cell for genus RTL synthesis. So how can i perform this including the standard cell to get criticle path delay and power
It wont be possible to change number of fingers , you can only set total width i nmos4 of nalog library. You will require tech lfiles from fab lab for that.
Watch the video carefully to know the correct directory where the model files are to be pasted. If problem still persists probably it has been locked by your administrator
@@SanjayVidhyadharan yes sir. It is locked by our administration.. is there any alternative sir. I already make cnfet by your stanford procedure only sir.
The model files generally specify Lmin and nominal VDD at top of the code. These are PTM models and not fab lab models and hence they don't specify all parameters. Minimum Width is generally 2.2 to 2.6 times L_min. Better option is to refer to tsmc data or microwind application data or other fab lab data .
Dear Sir, Thank you very much for your clarification. However, the PTM site is down and I would like to ask your help where I can get the 7nm cmos technology model. Thank you.
Just try on the net few instsitutions have now pu the ptm spice files on their web sites
I hope you reply early: the ptm website doesn't open for me. Do you have the data for the nmos and pmos somewhere else?
Kind regards,
Not sure about other web sites. Hope the site comes up soon.
I want to use transmission gate in my design but it is not available as standard cell for genus RTL synthesis. So how can i perform this including the standard cell to get criticle path delay and power
it it is not avaliale as a stanadard cell you may try making one gate with transistors. Not sure on how genus works
Sir please make a video on how to use 7nm ASAP PDK on both Virtuoso and Digital flow like genus and innovus
The PTM sie is down prsently. Hope it is restored soon.
Sir same as alekhya Im not getting correct output characteristics for 7nm ptm model.
Please veriry nmos and pmos device characteristics sepetaley first.
@@SanjayVidhyadharan thanks sir... please make tutorial for cadence to do band gap reference design...
Sir,is 7nm a cmos model or finfet model?
finfet
Sir can you please tell me where i can find the 7nm finfet file ,because the sight is not working
PTM is now avalible at many web sites for eaxmple mec.umn.edu/ptm
Ptm website is not there from the last few days ..
Sir where can we get the model files
Not sure about other web sites. Hope the site comes up soon.
sir thanks for the information can we get the gpdk 32nm libraries for cmos,
gdpk will avalible with Cadance. Not sure it is avalaible for free downlowad.
Thank you sir.....if we can't create layout for PTM files....then which tool ( Open source) can be used for calculating area for such PTM files sir?
You can try VLSI ELECTRIC. I have not tried it yet.
@@SanjayVidhyadharan Thank you sir
Hello sir, how can I change the finger number cause there is no such parameter in nmos4 in analoglib? Thanks
It wont be possible to change number of fingers , you can only set total width i nmos4 of nalog library. You will require tech lfiles from fab lab for that.
The link is not working can you plz check or can you share the library files
You may srching on the ineternet. It is now avlaible in website of few other unversities
why the link given is cant be access to the website?
That site I reffreed is no working. But there aree other now providing the fles. Google serach "ptm model files"
Not able to find the site
You may srching on the ineternet. It is now avlaible in website of few other unversities
when to use vdc and when to vpulse? please answer
VDC is for DC Power supply and Vpulse gives square/rectangular wave for transient analysis.
Thank you sir
Welcome
Very good
Thanks
Thank u so much sir. But how can we add these PTM files to tanner eda sir.
Sorry,, I haven't worked on tanner . I can help you out with cadence and LT spice
Sir, In cadence im not getting proper output characteristics for 7nm ptm model. i followed the same process as in video.kindly help sir.
can you mail me your problems in detail with snap shots and error message's
@@SanjayVidhyadharan sure sir. Thankyou.
Same .. I'm also getting error..
I am also getting same problem output characteristics is not proper. Did you get the solution from snajay Vidhyadhaaran
sir, is it possible to perform post-layout simulation using this ptm model file?
Layout is not possible with PTM model files
Layout is not possible with PTM model files
Sir, while paste the files in spectry it shows permission denied..
Watch the video carefully to know the correct directory where the model files are to be pasted. If problem still persists probably it has been locked by your administrator
@@SanjayVidhyadharan yes sir. It is locked by our administration.. is there any alternative sir. I already make cnfet by your stanford procedure only sir.
@@SanjayVidhyadharan sir, can you share your mail id. I will contact you regarding to this.
I am also getting same problem output characteristics is not proper. Please help me out sir. I have already mail you my circuit diagram and VTC curve.
Try nmos and pmos device characteristics first.
Sir, may we import finfet ptm also same procedure
Yes- you cam import infet ptm also following the same procedure
@@SanjayVidhyadharan thanks sir
Sir will you know the procedure for process corner procedure in Cadence for SRAM cell
@@SanjayVidhyadharan Hello sir, which is the PTM FinFET library? I'm looking for a 45nm FinFET PTM library.
sir what is the minimum width of pmos and nmos in 16 nm cmos technology
The model files generally specify Lmin and nominal VDD at top of the code. These are PTM models and not fab lab models and hence they don't specify all parameters. Minimum Width is generally 2.2 to 2.6 times L_min. Better option is to refer to tsmc data or microwind application data or other fab lab data .
Sir, can u please see the problem of my cadence system while paste these files through anydesk
Can you plesea mail me details at sanjayv@hyderabad.bits-pilani.ac.in
@@SanjayVidhyadharan sure sir. I will
sir, is it possible to import 45 nm in virtuoso
You can import 45 nm PTM files
Layout is not possible with PTM files
Its very important for me. Please respond as early as possible sir
Can you plesea mail me details at sanjayv@hyderabad.bits-pilani.ac.in