Sir , your lectures are very geartful and insight to learn the STA , i have query sir why STA is done only synchronous design and why not on asynchronous design . Query 2 why sta is not applicable to cdc .. Please kindly throw some light on cdc . Please kindly let me know sir . I will be thankful you sir
Hi Chandra, good questions. Hopefully one day I will make a detailed lecture on CDC, but I'm not sure when I will get to that. Q1: Why is STA only on synchronous design? Well the answer is basically the basis of all the algorithms and approaches we described. They are all related to some clock signal - something that synchronizes the paths that are racing each other. I am far from an expert on asynchronous design, but there too, we try to find means to verify and validate the paths and (possibly due to our "bias" towards synchronous STA), we take a lot of our knowledge and methods from STA and try to apply them. However, at the basis, the problem is not equivalent, since there is no clock as a reference that the other path is "racing" against. Q2: Why is STA not applicable to CDC? Here the problem lies in the clock source. CDC means you have paths that originate from two different clock sources with no (well defined) relation between them. Hence, even if we know the frequency of the clocks (for example, let's say they are at the same frequency), the phase between the two clocks could be anything. So we would have to look at the worst case of such a phase. For example, if we are looking at max delay, we can assume the phase delay (basically skew) is such that the capture clock rises 1ps after the launch clock, and we cannot meet timing with such a requirement. In other words, if you have a clock domain crossing, the only guarantee you have is that you will NOT MEET standard STA requirements. Therefore, in order to facilitate such situations, we must insert some barrier (e.g., synchronizer, FIFO, etc.) that ensures correct functionality without meeting max delay/min delay constraints of traditional STA.
Hi, A timing model is a simplification of how to calculate the delay (and a few other things) through a digital gate. This is fully covered in Lecture 3 of this series. Specifically, I suggest you watch this video: th-cam.com/video/akD4lC0deMk/w-d-xo.html
![[Live] : ONE 169 วันนี้!! "อนาโตลี vs อูมาร์"](http://i.ytimg.com/vi/IK3YZVWuFJg/mqdefault.jpg)
Again, a brillant video. 👍
Thank you! Cheers!
Sir , your lectures are very geartful and insight to learn the STA , i have query sir why STA is done only synchronous design and why not on asynchronous design .
Query 2 why sta is not applicable to cdc ..
Please kindly throw some light on cdc .
Please kindly let me know sir .
I will be thankful you sir
Hi Chandra, good questions.
Hopefully one day I will make a detailed lecture on CDC, but I'm not sure when I will get to that.
Q1: Why is STA only on synchronous design? Well the answer is basically the basis of all the algorithms and approaches we described. They are all related to some clock signal - something that synchronizes the paths that are racing each other. I am far from an expert on asynchronous design, but there too, we try to find means to verify and validate the paths and (possibly due to our "bias" towards synchronous STA), we take a lot of our knowledge and methods from STA and try to apply them. However, at the basis, the problem is not equivalent, since there is no clock as a reference that the other path is "racing" against.
Q2: Why is STA not applicable to CDC?
Here the problem lies in the clock source. CDC means you have paths that originate from two different clock sources with no (well defined) relation between them. Hence, even if we know the frequency of the clocks (for example, let's say they are at the same frequency), the phase between the two clocks could be anything. So we would have to look at the worst case of such a phase. For example, if we are looking at max delay, we can assume the phase delay (basically skew) is such that the capture clock rises 1ps after the launch clock, and we cannot meet timing with such a requirement. In other words, if you have a clock domain crossing, the only guarantee you have is that you will NOT MEET standard STA requirements.
Therefore, in order to facilitate such situations, we must insert some barrier (e.g., synchronizer, FIFO, etc.) that ensures correct functionality without meeting max delay/min delay constraints of traditional STA.
@@AdiTeman thank you sir .
could you please say what is timing model?
Hi,
A timing model is a simplification of how to calculate the delay (and a few other things) through a digital gate. This is fully covered in Lecture 3 of this series. Specifically, I suggest you watch this video: th-cam.com/video/akD4lC0deMk/w-d-xo.html