DVCon Europe 2021 - Sessions P3.4, P3.5, P3.6

Presented at DVCon Europe 2021
This video consists of three presentations.
-- A Comparison of Methodologies to Simulate Mixed-signal IC
By Simone Fontanesi¹; Paul Ehrlich²; Karsten Einwich²; Gaetano Formato¹; Andrea Possemato¹
¹ Infineon Technologies Austria AG; ² COSEDA Technologies GmbH
-- Unified Model/Hardware-in-the-Loop Methodology for Mixed-Signal System Design and Hardware Prototyping
By Martin Barnasconi¹; Wil Kitzen¹; Thieu Lammers¹; Paul Ehrlich²; Karsten Einwich² ¹ NXP Semiconductors; ² COSEDA Technologies GmbH
-- Accelerated Coverage Closure by Utilizing Local Structure in the RTL Code
By Gokce Sarar¹; Guillaume Shippee¹; Tushit Jain¹; Rhys Buggy²; Vishal Karna¹; Han Nuon¹
¹ Qualcomm Technologies, Inc.; ² QT Technologies Ireland Limited
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